Reintroduce original Zybo + HDMI addition (#461)

* Reintroduce original Zybo support

* Reintroduce original zybo, add HDMI + fixes for Z7

litex_boards/platforms/digilent_zybo_z7.py

@@ -2,6 +2,7 @@
 # This file is part of LiteX-Boards.
 #
 # Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
+# Copyright (c) 2022 Oliver Szabo <16oliver16@gmail.com>
 # SPDX-License-Identifier: BSD-2-Clause
 
 from litex.build.generic_platform import *
@@ -9,10 +10,31 @@ from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer
 
 # IOs ----------------------------------------------------------------------------------------------
 
-_io = [
+_io_z7 = [
     # Clk / Rst
     ("clk125", 0, Pins("K17"), IOStandard("LVCMOS33")),
 
+    # Buttons
+    ("user_btn", 0, Pins("K18"), IOStandard("LVCMOS33")),
+    ("user_btn", 1, Pins("P16"), IOStandard("LVCMOS33")),
+    ("user_btn", 2, Pins("K19"), IOStandard("LVCMOS33")),
+    ("user_btn", 3, Pins("Y16"), IOStandard("LVCMOS33")),
+  
+]
+
+_io_original = [
+    # Clk / Rst
+    ("clk125", 0, Pins("L16"), IOStandard("LVCMOS33")),
+
+    # Buttons
+    ("user_btn", 0, Pins("R18"), IOStandard("LVCMOS33")),
+    ("user_btn", 1, Pins("P16"), IOStandard("LVCMOS33")),
+    ("user_btn", 2, Pins("V16"), IOStandard("LVCMOS33")),
+    ("user_btn", 3, Pins("Y16"), IOStandard("LVCMOS33")),
+
+]
+
+_io = [
     # Leds
     ("user_led", 0, Pins("M14"), IOStandard("LVCMOS33")),
     ("user_led", 1, Pins("M15"), IOStandard("LVCMOS33")),
@@ -25,11 +47,21 @@ _io = [
     ("user_sw", 2, Pins("W13"), IOStandard("LVCMOS33")),
     ("user_sw", 3, Pins("T16"), IOStandard("LVCMOS33")),
 
-    # Buttons
+    # HDMI Out
-    ("user_btn", 0, Pins("R18"), IOStandard("LVCMOS33")),
+    ("hdmi_out", 0,
-    ("user_btn", 1, Pins("P16"), IOStandard("LVCMOS33")),
+        Subsignal("clk_p",   Pins("H16"), IOStandard("TMDS_33")),
-    ("user_btn", 2, Pins("V16"), IOStandard("LVCMOS33")),
+        Subsignal("clk_n",   Pins("H17"), IOStandard("TMDS_33")),
-    ("user_btn", 3, Pins("Y16"), IOStandard("LVCMOS33")),
+        Subsignal("data0_p", Pins("D19"), IOStandard("TMDS_33")),
+        Subsignal("data0_n", Pins("D20"), IOStandard("TMDS_33")),
+        Subsignal("data1_p", Pins("C20"), IOStandard("TMDS_33")),
+        Subsignal("data1_n", Pins("B20"), IOStandard("TMDS_33")),
+        Subsignal("data2_p", Pins("B19"), IOStandard("TMDS_33")),
+        Subsignal("data2_n", Pins("A20"), IOStandard("TMDS_33")),
+        Subsignal("scl",     Pins("G17"), IOStandard("LVCMOS33")),
+        Subsignal("sda",     Pins("G18"), IOStandard("LVCMOS33")),
+        Subsignal("cec",     Pins("E19"), IOStandard("LVCMOS33")),
+        Subsignal("hdp",     Pins("E18"), IOStandard("LVCMOS33")),
+    ),
 
     # Serial
     ("serial", 0,
@@ -78,17 +110,23 @@ _usb_uart_pmod_io = [
 
 # Connectors ---------------------------------------------------------------------------------------
 
+_connectors_z7 = [
+    ("pmodb", "V8  W8  U7  V7  Y7  Y6  V6  W6")
+]
+
 _connectors = [
     ("pmoda", "N15 L14 K16 K14 N16 L15 J16 J14"), # XADC
-    ("pmodb", "V8  W8  U7  V7  Y7  Y6  V6  W6"),
     ("pmodc", "V15 W15 T11 T10 W14 Y14 T12 U12"),
     ("pmodd", "T14 T15 P14 R14 U14 U15 V17 V18"),
     ("pmode", "V12 W16 J15 H15 V13 U17 T17 Y17"),
 ]
 
-ps7_config = {
+_connectors_original = [
-    "z7-20" : {
+    ("pmodb", "T20  U20  V20  W20  Y18  Y19  W18  W19")
-        "PCW_UIPARAM_DDR_PARTNO"        : "MT41K256M16 RE-125",
+]
+
+ps7_config_variants = {
+    "common" : {
         "PCW_FPGA_FCLK0_ENABLE"         : "1",
         "PCW_UART1_BAUD_RATE"           : "115200",
         "PCW_EN_UART1"                  : "1",
@@ -102,6 +140,12 @@ ps7_config = {
         "PCW_USB0_RESET_ENABLE"         : "1",
         "PCW_USB0_RESET_IO"             : "MIO 46",
         "PCW_EN_USB0"                   : "1"
+    },
+    "z7" : {
+        "PCW_UIPARAM_DDR_PARTNO"        : "MT41K256M16 RE-125"
+    },
+    "original" : {
+        "PCW_UIPARAM_DDR_PARTNO"        : "MT41K128M16 RE-125"
     }
 }
 # Platform -----------------------------------------------------------------------------------------
@@ -113,12 +157,22 @@ class Platform(Xilinx7SeriesPlatform):
     def __init__(self, variant="z7-20", toolchain="vivado"):
         device = {
             "z7-10": "xc7z010-clg400-1",
-            "z7-20": "xc7z020-clg400-1"
+            "z7-20": "xc7z020-clg400-1",
+            "original": "xc7z010-clg400-1"
         }[variant]
+        ps7_config = ps7_config_variants["common"]
+        if variant == "original":
+            _connectors = _connectors + _connectors_original
+            _io = _io + _io_original
+            ps7_config.update(ps7_config_variants["original"])
+        else:
+            _connectors = _connectors + _connectors_z7
+            _io = _io + _io_z7
+            ps7_config.update(ps7_config_variants["z7"])
         Xilinx7SeriesPlatform.__init__(self, device, _io,  _connectors, toolchain=toolchain)
         self.add_extension(_ps7_io)
         self.add_extension(_usb_uart_pmod_io)
-        self.ps7_config = ps7_config[variant]
+        self.ps7_config = ps7_config
 
     def create_programmer(self):
         return VivadoProgrammer()

litex_boards/targets/xilinx_zybo_z7.py

@@ -3,7 +3,8 @@
 #
 # This file is part of LiteX-Boards.
 #
-# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>,
+# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
+# Copyright (c) 2022 Oliver Szabo <16oliver16@gmail.com>
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
@@ -59,12 +60,12 @@ class BaseSoC(SoCCore):
             self.mem_map = {
                 'csr': 0x4000_0000,  # Zynq GP0 default
             }
-        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Zybo Z7", **kwargs)
+        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Zybo Z7/original Zybo", **kwargs)
 
         # Zynq7000 Integration ---------------------------------------------------------------------
         if kwargs.get("cpu_type", None) == "zynq7000":
             self.cpu.use_rom = True
-            if variant == "z7-10":
+            if variant in ["z7-20", "original"]:
                 # Get and set the pre-generated .xci FIXME: change location? add it to the repository? Make config
                 os.makedirs("xci", exist_ok=True)
                 os.system("wget https://github.com/litex-hub/litex-boards/files/8339591/zybo_z7_ps7.txt")
@@ -99,7 +100,7 @@ class BaseSoC(SoCCore):
 
         # PS7 as Slave Integration ---------------------------------------------------------------------
         elif with_ps7:
-            if variant == "z7-20":
+            if variant in ["z7-20", "original"]:
                 cpu_cls = cpu.CPUS["zynq7000"]
                 zynq    = cpu_cls(self.platform, "standard") # zynq7000 has no variants
                 zynq.set_ps7(name="ps", config = platform.ps7_config)
@@ -170,9 +171,9 @@ class BaseSoC(SoCCore):
 
 def main():
     from litex.build.parser import LiteXArgumentParser
-    parser = LiteXArgumentParser(platform=digilent_zybo_z7.Platform, description="LiteX SoC on Zybo Z7")
+    parser = LiteXArgumentParser(platform=digilent_zybo_z7.Platform, description="LiteX SoC on Zybo Z7/original Zybo")
     parser.add_target_argument("--sys-clk-freq",    default=125e6, type=float,  help="System clock frequency.")
-    parser.add_target_argument("--variant",         default="z7-10",            help="Board variant (z7-10 or z7-20).")
+    parser.add_target_argument("--variant",         default="z7-10",            help="Board variant (z7-10, z7-20 or original).")
     parser.add_target_argument("--with-ps7",        action="store_true",        help="Add the PS7 as slave for soft CPUs.")
     args = parser.parse_args()