Hardware/litex-boards
1
0
Fork 0
mirror of https://github.com/litex-hub/litex-boards.git synced 2025-01-03 03:43:36 -05:00
Code Issues Projects Releases Packages Wiki Activity

mnt_rkx7: Cosmetic cleanups.

Browse source
This commit is contained in:
Florent Kermarrec 2023-05-05 09:48:06 +02:00
parent c05c494a82
commit d33cf1a74c
2 changed files with 29 additions and 25 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
litex_boards/platforms/mnt_rkx7.py
View file

@ -26,7 +26,7 @@ _io = [
Subsignal("rx", Pins("G16")), Subsignal("rx", Pins("G16")),
IOStandard("LVCMOS33") IOStandard("LVCMOS33")
), ),
("litescope_serial", 0, ("debug_serial", 0,
Subsignal("tx", Pins("C17")), Subsignal("tx", Pins("C17")),
Subsignal("rx", Pins("C16")), Subsignal("rx", Pins("C16")),
IOStandard("LVCMOS33") IOStandard("LVCMOS33")

52
litex_boards/targets/mnt_rkx7.py
View file

@ -8,23 +8,25 @@
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
from migen import * from migen import *
from migen.fhdl.specials import Tristate
from litex.gen import * from litex.gen import *
from litex_boards.platforms import mnt_rkx7 from litex_boards.platforms import mnt_rkx7
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.soc import SoCRegion from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr import *
from litex.soc.interconnect.axi import * from litex.soc.interconnect.axi import *
from litex.soc.interconnect.wishbone import * from litex.soc.interconnect.wishbone import *
from litex.soc.cores.clock import *
from litex.soc.cores.bitbang import I2CMaster from litex.soc.cores.bitbang import I2CMaster
from litex.soc.cores.gpio import GPIOOut from litex.soc.cores.gpio import GPIOOut
from litex.soc.cores.video import VideoDVIPHY from litex.soc.cores.video import VideoDVIPHY
from litex.soc.cores.usb_ohci import USBOHCI from litex.soc.cores.usb_ohci import USBOHCI
from migen.fhdl.specials import Tristate
from litedram.modules import IS43TR16512B from litedram.modules import IS43TR16512B
from litedram.phy import s7ddrphy from litedram.phy import s7ddrphy
@ -84,6 +86,7 @@ class BaseSoC(SoCCore):
with_etherbone = False, with_etherbone = False,
with_spi_flash = True, with_spi_flash = True,
with_usb_host = True, with_usb_host = True,
with_analyzer = False,
**kwargs): **kwargs):
platform = mnt_rkx7.Platform() platform = mnt_rkx7.Platform()
@ -177,28 +180,29 @@ class BaseSoC(SoCCore):
dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma) dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma)
self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt) self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt)
# LiteScope UART # LiteScope Analyzer -----------------------------------------------------------------------
self.add_uartbone(name="litescope_serial") if with_analyzer:
# LiteScope Analyzer (optional) from litescope import LiteScopeAnalyzer
# analyzer_signals = [ self.add_uartbone(name="debug_serial")
# ulpi_data.din, analyzer_signals = [
# utmi.linestate, ulpi_data.din,
# utmi.txvalid, utmi.linestate,
# utmi.rxerror, utmi.txvalid,
# utmi.rxvalid, utmi.rxerror,
# usb_ulpi.dir, utmi.rxvalid,
# usb_ulpi.stp, usb_ulpi.dir,
# usb_ulpi.nxt, usb_ulpi.stp,
# usbh_dbg_state, usb_ulpi.nxt,
# ulpi_dbg_state, usbh_dbg_state,
# usb_host_intr, ulpi_dbg_state,
# usb_host_dbg_intr, usb_host_intr,
# ] usb_host_dbg_intr,
# from litescope import LiteScopeAnalyzer ]
# self.analyzer = LiteScopeAnalyzer(analyzer_signals, self.analyzer = LiteScopeAnalyzer(analyzer_signals,
# depth = 256, depth = 256,
# clock_domain = "ulpi", clock_domain = "ulpi",
# csr_csv = "analyzer.csv") csr_csv = "analyzer.csv"
)
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------