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Merge pull request #100 from connorwk/master 

Changes to acorn-cle-215 platform/target files.
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enjoy-digital 2020-08-22 22:04:52 +02:00 committed by GitHub
parent 45bb329b56 f328909578
commit d365836af5
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2 changed files with 24 additions and 8 deletions
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10
litex_boards/platforms/acorn_cle_215.py
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@ -33,6 +33,16 @@ _io = [
IOStandard("LVCMOS33") IOStandard("LVCMOS33")
), ),
# spisdcard (requires adapter off P2)
("spisdcard", 0,
Subsignal("clk", Pins("J2")),
Subsignal("mosi", Pins("J5"), Misc("PULLUP True")),
Subsignal("cs_n", Pins("H5"), Misc("PULLUP True")),
Subsignal("miso", Pins("K2"), Misc("PULLUP True")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS33"),
),
# pcie # pcie
("pcie_clkreq_n", 0, Pins("G1"), IOStandard("LVCMOS33")), ("pcie_clkreq_n", 0, Pins("G1"), IOStandard("LVCMOS33")),
("pcie_x4", 0, ("pcie_x4", 0,

22
litex_boards/targets/acorn_cle_215.py
View File

@ -70,7 +70,8 @@ class CRG(Module):
# BaseSoC ----------------------------------------------------------------------------------------- # BaseSoC -----------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, platform, with_pcie=False, **kwargs): def __init__(self, with_pcie=False, **kwargs):
platform = acorn_cle_215.Platform()
sys_clk_freq = int(100e6) sys_clk_freq = int(100e6)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
@ -158,11 +159,12 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Acorn CLE 215+") parser = argparse.ArgumentParser(description="LiteX SoC on Acorn CLE 215+")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support (requires adapter off P2)")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
parser.add_argument("--flash", action="store_true", help="Flash bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--flash", action="store_true", help="Flash bitstream")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
@ -170,11 +172,15 @@ def main():
# Enforce arguments # Enforce arguments
args.csr_data_width = 32 args.csr_data_width = 32
platform = acorn_cle_215.Platform() soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args))
soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)
if args.driver: if args.driver:
generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver")) generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))