Merge pull request #395 from AEW2015/master
Support for "discontinued" Avnet aes-ku040-db-g development board
This commit is contained in:
enjoy-digital
GitHub
commit
d37af4aece
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@ -105,6 +105,7 @@ Some of the suported boards, see yours? Give LiteX-Boards a try!
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├── antmicro_lpddr4_test_board
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├── arduino_mkrvidor4000
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├── avalanche
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├── avnet_aesku40
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├── berkeleylab_marblemini
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├── berkeleylab_marble
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├── camlink_4k
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@ -0,0 +1,199 @@
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Andrew Elbert Wilson <andrew.e.wilson@ieee.org>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk250", 0,
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Subsignal("p", Pins("H22"), IOStandard("LVDS")),
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Subsignal("n", Pins("H23"), IOStandard("LVDS"))
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),
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("cpu_reset", 0, Pins("N24"), IOStandard("LVCMOS12")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("D20")),
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Subsignal("rx", Pins("C19")),
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IOStandard("LVCMOS18")
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),
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# MII Ethernet
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("eth_clocks", 0,
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Subsignal("tx", Pins("G10")),
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Subsignal("rx", Pins("E11")),
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IOStandard("LVCMOS18")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("D9")),
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#Subsignal("int_n", Pins("Y14")),
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Subsignal("mdio", Pins("C8")),
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Subsignal("mdc", Pins("C9")),
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Subsignal("rx_ctl", Pins("D11")),
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Subsignal("rx_data", Pins("A10 B10 B11 C11")),
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Subsignal("tx_ctl", Pins("G9")),
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Subsignal("tx_data", Pins("H8 H9 J9 J10")),
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IOStandard("LVCMOS18")
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),
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# DDR4 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"AA24 AB24 AB26 AC26 AA22 AB22 Y23 AA23",
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"AC23 AC24 W23 W24 W25 W26"),
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IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("V26 U24"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("V24"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("U26"), IOStandard("SSTL12_DCI")), # A16
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Subsignal("cas_n", Pins("Y26"), IOStandard("SSTL12_DCI")), # A15
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Subsignal("we_n", Pins("Y25"), IOStandard("SSTL12_DCI")), # A14
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Subsignal("cs_n", Pins("V22"), IOStandard("SSTL12_DCI")),
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Subsignal("act_n", Pins("T24"), IOStandard("SSTL12_DCI")),
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#Subsignal("ten", Pins("AH16"), IOStandard("SSTL12_DCI")),
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#Subsignal("alert_n", Pins("AJ16"), IOStandard("SSTL12_DCI")),
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#Subsignal("par", Pins("AD18"), IOStandard("SSTL12_DCI")),
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Subsignal("dm", Pins("T23 R18 N23 E25"),
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IOStandard("POD12_DCI")),
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Subsignal("dq", Pins(
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"T22 U22 P26 R26 P23 P24 P25 R25",
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"P21 R21 P18 P19 P20 R20 U20 U21",
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"N26 M26 M24 L24 N22 M22 M25 L25",
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"H26 G26 G25 F25 J24 J25 H24 G24"),
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IOStandard("POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_p", Pins("R22 T19 K26 F22"),
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IOStandard("DIFF_POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_n", Pins("R23 T20 J26 F23"),
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IOStandard("DIFF_POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("clk_p", Pins("AA25"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("clk_n", Pins("AB25"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("cke", Pins("V23"), IOStandard("SSTL12_DCI")),
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Subsignal("odt", Pins("U25"), IOStandard("SSTL12_DCI")),
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Subsignal("reset_n", Pins("T25"), IOStandard("LVCMOS12")),
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Misc("SLEW=FAST"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("pmod0", "J13 H13 A13 A12 C12 B12 D13 C13"),
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("pmod1", "F9 F8 E8 D8 E10 D10 G12 F12"),
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]
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# PMODS --------------------------------------------------------------------------------------------
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def raw_pmod_io(pmod):
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return [(pmod, 0, Pins(" ".join([f"{pmod}:{i:d}" for i in range(8)])), IOStandard("LVCMOS33"))]
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def usb_pmod_io(pmod):
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return [
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# USB-UART PMOD: https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/
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("usb_uart", 0,
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Subsignal("tx", Pins(f"{pmod}:1")),
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Subsignal("rx", Pins(f"{pmod}:2")),
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IOStandard("LVCMOS18")
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),
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]
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_usb_uart_pmod_io = usb_pmod_io("pmod0") # USB-UART PMOD on JB.
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def i2s_pmod_io(pmod):
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return [
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# I2S PMOD: https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/
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("i2s_rx_mclk", 0, Pins(f"{pmod}:4"), IOStandard("LVCMOS33")),
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("i2s_rx", 0,
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Subsignal("clk", Pins(f"{pmod}:6")),
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Subsignal("sync", Pins(f"{pmod}:5")),
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Subsignal("rx", Pins(f"{pmod}:7")),
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IOStandard("LVCMOS18"),
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),
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("i2s_tx_mclk", 0, Pins(f"{pmod}:0"), IOStandard("LVCMOS33")),
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("i2s_tx", 0,
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Subsignal("clk",Pins(f"{pmod}:2")),
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Subsignal("sync", Pins(f"{pmod}:1")),
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Subsignal("tx", Pins(f"{pmod}:3")),
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IOStandard("LVCMOS18"),
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),
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]
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_i2s_pmod_io = i2s_pmod_io("pmod0") # I2S PMOD on JA.
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def sdcard_pmod_io(pmod):
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return [
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# SDCard PMOD:
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# - https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
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# - https://github.com/antmicro/arty-expansion-board
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("spisdcard", 0,
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Subsignal("clk", Pins(f"{pmod}:3")),
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Subsignal("mosi", Pins(f"{pmod}:1"), Misc("PULLUP True")),
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Subsignal("cs_n", Pins(f"{pmod}:0"), Misc("PULLUP True")),
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Subsignal("miso", Pins(f"{pmod}:2"), Misc("PULLUP True")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS18"),
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),
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("sdcard", 0,
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Subsignal("data", Pins(f"{pmod}:2 {pmod}:4 {pmod}:5 {pmod}:0"), Misc("PULLUP True")),
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Subsignal("cmd", Pins(f"{pmod}:1"), Misc("PULLUP True")),
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Subsignal("clk", Pins(f"{pmod}:3")),
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Subsignal("cd", Pins(f"{pmod}:6")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS18"),
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),
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]
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_sdcard_pmod_io = sdcard_pmod_io("pmod0") # SDCARD PMOD on JD.
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def numato_sdcard_pmod_io(pmod):
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return [
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# SDCard PMOD:
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# https://numato.com/product/micro-sd-expansion-module/
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# This adaptor does not have the card detect (CD) pin connected
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("spisdcard", 0,
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Subsignal("clk", Pins(f"{pmod}:5")),
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Subsignal("mosi", Pins(f"{pmod}:1"), Misc("PULLUP True")),
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Subsignal("cs_n", Pins(f"{pmod}:4"), Misc("PULLUP True")),
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Subsignal("miso", Pins(f"{pmod}:2"), Misc("PULLUP True")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS18"),
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),
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("sdcard", 0,
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Subsignal("data", Pins(f"{pmod}:2 {pmod}:6 {pmod}:0 {pmod}:4"), Misc("PULLUP True")),
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Subsignal("cmd", Pins(f"{pmod}:1"), Misc("PULLUP True")),
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Subsignal("clk", Pins(f"{pmod}:5")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS18"),
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),
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]
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_numato_sdcard_pmod_io = numato_sdcard_pmod_io("pmod0") # SDCARD PMOD on JD.
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk250"
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default_clk_period = 1e9/250e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xcku040-fbva676-1-c", _io, _connectors, toolchain="vivado")
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk250", loose=True), 1e9/250e6)
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 44]")
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 45]")
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@ -0,0 +1,135 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Andrew Elbert Wilson <andrew.e.wilson@ieee.org>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import avnet_aesku40
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import EDY4016A
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from litedram.phy import usddrphy
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from liteeth.phy.ku_1000basex import KU_1000BASEX
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from litepcie.phy.uspciephy import USPCIEPHY
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from litepcie.software import generate_litepcie_software
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from liteeth.phy.usrgmii import LiteEthPHYRGMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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# # #
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self.submodules.pll = pll = USMMCM(speedgrade=-2)
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self.comb += pll.reset.eq(platform.request("cpu_reset") | self.rst)
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pll.register_clkin(platform.request("clk250"), 250e6)
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_idelay, 200e6)
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pll.create_clkout(self.cd_eth, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.specials += [
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Instance("BUFGCE_DIV", name="main_bufgce_div",
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p_BUFGCE_DIVIDE=4,
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
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Instance("BUFGCE", name="main_bufgce",
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
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]
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self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False,
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eth_ip="192.168.1.50", with_led_chaser=True, with_pcie=False, with_sata=False,
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**kwargs):
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platform = avnet_aesku40.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on AESKU40",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# Ethernet ---------------------------------------------------------------------------------
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if with_ethernet:
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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tx_delay=1e-9, #Supported Delay with 200 MHz ref clk
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rx_delay=1e-9)
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#Change ref clk for idelay3s
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for special in self.ethphy.rx._fragment.specials:
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if special.name_override == "IDELAYE3":
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for item in special.items:
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if item.name == "REFCLK_FREQUENCY":
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item.value=200.00
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self.add_ethernet(phy=self.ethphy)
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# DDR4 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
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memtype = "DDR4",
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 200e6)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = EDY4016A(sys_clk_freq, "1:4"),
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size = 0x40000000,
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on AESKU40")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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