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Merge pull request #374 from smunaut/adrv2crr 

adi_adrv2crr: Upgrade part to speedgrade 2
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enjoy-digital 2022-03-23 09:09:57 +01:00 committed by GitHub
parent 4ca527974b dc92584681
commit d399f33dda
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2
litex_boards/platforms/adi_adrv2crr_fmc.py
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@ -476,7 +476,7 @@ class Platform(XilinxPlatform):
default_clk_period = 1e9/122.88e6 default_clk_period = 1e9/122.88e6
def __init__(self): def __init__(self):
XilinxPlatform.__init__(self, "xczu11eg-ffvf1517-1-i", _io, _connectors, toolchain="vivado") XilinxPlatform.__init__(self, "xczu11eg-ffvf1517-2-i", _io, _connectors, toolchain="vivado")
def do_finalize(self, fragment): def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment) XilinxPlatform.do_finalize(self, fragment)