platforms/acorn_cle_215: add serial_io (on P2).
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@ -76,6 +76,16 @@ _io = [
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),
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),
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]
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]
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_serial_io = [
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# Serial adapter on P2
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("serial", 0,
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Subsignal("tx", Pins("K2")),
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Subsignal("rx", Pins("J2")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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_sdcard_io = [
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_sdcard_io = [
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# SPI SDCard adapter on P2
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# SPI SDCard adapter on P2
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# https://spoolqueue.com/new-design/fpga/migen/litex/2020/08/11/acorn-cle-215.html
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# https://spoolqueue.com/new-design/fpga/migen/litex/2020/08/11/acorn-cle-215.html
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@ -97,6 +107,7 @@ class Platform(XilinxPlatform):
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def __init__(self):
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, toolchain="vivado")
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XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, toolchain="vivado")
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self.add_extension(_serial_io)
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self.add_extension(_sdcard_io)
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self.add_extension(_sdcard_io)
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
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