Merge pull request #431 from mntmn/master
MNT RKX7: update platform and target for D-2 release
This commit is contained in:
commit
d6dadb6058
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@ -2,6 +2,7 @@
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2022 Lukas F. Hartmann, MNT Research GmbH <lukas@mntre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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@ -20,6 +21,16 @@ _io = [
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Subsignal("rx", Pins("C18")),
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IOStandard("LVCMOS33")
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),
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("serial", 1,
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Subsignal("tx", Pins("H16")),
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Subsignal("rx", Pins("G16")),
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IOStandard("LVCMOS33")
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),
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("litescope_serial", 0,
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Subsignal("tx", Pins("C17")),
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Subsignal("rx", Pins("C16")),
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IOStandard("LVCMOS33")
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),
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# SPIFlash
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("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
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@ -66,30 +77,51 @@ _io = [
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# I2C
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("i2c", 0,
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Subsignal("scl", Pins("Y26")),
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Subsignal("sda", Pins("W26")),
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IOStandard("LVCMOS18"),
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),
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("i2c", 1,
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Subsignal("scl", Pins("G12")),
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Subsignal("sda", Pins("A13")),
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IOStandard("LVCMOS18"),
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),
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("i2c", 2,
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Subsignal("scl", Pins("H26")),
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Subsignal("sda", Pins("G26")),
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IOStandard("LVCMOS33"),
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),
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# GPIO
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("resets", 0,
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Pins("M21 M22 C13 C14"), # Backlight PWM, Backlight EN, hdmi_rst_n, edp_reset_n
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IOStandard("LVCMOS18")
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),
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("gpio", 0,
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Pins("D13 N19 M19"), # USB hub reset, Analogix reset, eDP HPD
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IOStandard("LVCMOS18")
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),
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# DDR3 SDRAM.
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("ddram", 0,
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Subsignal("a", Pins(
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"AC8 AA7 AA8 AF7 AE7 AC11 V9 Y10",
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"AB11 Y7 Y8 V11 V8 W11 Y11 V7 "),
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"AC8 AA9 AA7 AD9 Y8 AA8 W11 Y10",
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"Y11 Y7 AC11 V11 AB11 V7 V9 V8"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("AC7 AB7 AB9"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("AA9"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AD8"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("AF7"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AE7"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AC9"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("AD9"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("AD8"), IOStandard("SSTL15")),
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Subsignal("dm", Pins(
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"U6 Y3 AB6 AD4"),
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IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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" V4 W3 U5 U1 U7 U2 V6 V3",
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" V4 W3 U5 U2 U7 U1 V6 V3",
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" Y2 Y1 AA3 V2 AC2 W1 AB2 V1",
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"AA4 AB4 AC4 AC3 AC6 Y6 Y5 AD6",
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"AD1 AE1 AE3 AE2 AE6 AE5 AF3 AF2"),
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"AA4 AB4 AC4 AC3 AC6 Y6 Y5 AD6",
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"AD1 AE1 AE3 AE2 AE6 AE5 AF3 AF2"
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),
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IOStandard("SSTL15_T_DCI")),
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Subsignal("dqs_p", Pins("W6 AB1 AA5 AF5"),
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IOStandard("DIFF_SSTL15")),
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@ -103,6 +135,53 @@ _io = [
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Misc("SLEW=FAST"),
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Misc("VCCAUX_IO=HIGH")
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),
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# HDMI (DISP1)
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("hdmi", 0,
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Subsignal("clk", Pins("C12")),
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Subsignal("de", Pins("D10")),
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Subsignal("hsync_n", Pins("D11")),
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Subsignal("vsync_n", Pins("E11")),
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Subsignal("b", Pins("H13 G10 J13 H12 J10 H8 H9 J11")), # [16:23]
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Subsignal("g", Pins("F14 C9 G14 F10 H14 G11 H11 G9")), # [8:15]
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Subsignal("r", Pins("E10 D8 F9 F8 A9 A8 B9 D9")), # [0:7]
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IOStandard("LVCMOS18")
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),
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# RGB->eDP (DISP2)
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("edp", 0,
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Subsignal("clk", Pins("AC18")),
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Subsignal("de", Pins("AA15")),
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Subsignal("hsync", Pins("AB15")), # hsync_n for negative
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Subsignal("vsync", Pins("AB16")), # vsync_n for negative
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Subsignal("b", Pins("AF14 AF15 AE15 AE16 AF17 AE17 AA14 AF18")), # [16:23]
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Subsignal("g", Pins("AD15 AE18 AD16 AF19 AC16 AD14 AC17 AC14")), # [8:15]
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Subsignal("r", Pins("AB14 Y15 AA17 AA18 Y16 AF20 AD20 AB17")), # [0:7]
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IOStandard("LVCMOS18"), Misc("DRIVE=4"),
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),
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("edpoff", 0,
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Pins("AD18"),
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IOStandard("LVCMOS18")
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),
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# Backlight via Motherboard (unused)
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("backlight", 0,
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Subsignal("pwm", Pins("K16")),
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Subsignal("en", Pins("B16")),
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IOStandard("LVCMOS33")
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),
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# USB
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("usb", 0,
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Subsignal("dp", Pins("D26")),
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Subsignal("dm", Pins("C26")),
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IOStandard("LVCMOS33"),
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),
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("usb_pull", 0,
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Pins("F25"),
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IOStandard("LVCMOS33")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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@ -117,6 +196,13 @@ class Platform(XilinxPlatform):
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def __init__(self, toolchain="vivado"):
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XilinxPlatform.__init__(self, "xc7k325t-ffg676-2", _io, _connectors, toolchain=toolchain)
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# Enable bitstream compression, quad SPI and 50MHz rate for quick boot from SPI flash
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# see https://github.com/timvideos/litex-buildenv/issues/79
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self.toolchain.bitstream_commands = [
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]"
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]
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit")
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@ -4,6 +4,7 @@
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2022 Lukas F. Hartmann, MNT Research GmbH <lukas@mntre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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@ -12,8 +13,16 @@ from litex_boards.platforms import mnt_rkx7
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect.axi import *
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from litex.soc.interconnect.wishbone import *
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from litex.soc.cores.bitbang import I2CMaster
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from litex.soc.cores.gpio import GPIOOut
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from litex.soc.cores.video import VideoDVIPHY
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from litex.soc.cores.usb_ohci import USBOHCI
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from migen.fhdl.specials import Tristate
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from litedram.modules import IS43TR16512B
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from litedram.phy import s7ddrphy
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@ -28,24 +37,44 @@ class _CRG(Module):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain()
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self.clock_domains.cd_idelay = ClockDomain()
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self.clock_domains.cd_dvi = ClockDomain(reset_less=True)
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self.clock_domains.cd_usb = ClockDomain()
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# # #
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clkin = platform.request("clk100")
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self.submodules.pll = pll = S7MMCM(speedgrade=-2)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request("clk100"), 100e6)
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# Main clock input (100MHz)
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pll.register_clkin(clkin, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_idelay, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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# Ignore sys_clk to pll.clkin path created by SoC's rst.
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
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# USB clock
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pll.create_clkout(self.cd_usb, 48e6)
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self.submodules.pll2 = pll2 = S7MMCM(speedgrade=-2)
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self.comb += pll2.reset.eq(self.rst)
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pll2.register_clkin(clkin, 100e6)
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# DVI/HDMI pixel clock
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pll2.create_clkout(self.cd_dvi, 80e6) # display wants 162e6, but we can underclock
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platform.add_false_path_constraints(self.cd_sys.clk, pll2.clkin)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False,
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with_spi_flash=False, **kwargs):
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mem_map = {**SoCCore.mem_map, **{
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# FIXME: ends up as 0x7f000000 in linux
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"video_framebuffer": 0x3f000000,
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"usb_ohci": 0xc0000000,
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}}
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def __init__(self, sys_clk_freq=int(100e6), with_ethernet=True, with_etherbone=False,
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with_spi_flash=True, **kwargs):
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platform = mnt_rkx7.Platform()
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# CRG --------------------------------------------------------------------------------------
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@ -64,7 +93,7 @@ class BaseSoC(SoCCore):
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phy = self.ddrphy,
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module = IS43TR16512B(sys_clk_freq, "1:4"),
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size = 0x40000000,
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_size = kwargs.get("l2_size", 8192), # TBD: is L2 really necessary?
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)
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# SPI Flash --------------------------------------------------------------------------------
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@ -79,13 +108,74 @@ class BaseSoC(SoCCore):
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {{main_ethphy_eth_rx_clk_ibuf}}]")
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platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {{soclinux_ethphy_eth_rx_clk_ibuf}}]")
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy)
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self.add_ethernet(phy=self.ethphy, dynamic_ip=True, software_debug=False)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy)
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# I2C --------------------------------------------------------------------------------------
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self.submodules.i2c = I2CMaster(platform.request("i2c"))
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# GPIO -------------------------------------------------------------------------------------
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# Controllable as faux "leds"
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# These are reset pins of various chips
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# We toggle them in LiteX BIOS
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reset_signals = platform.request("resets")
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self.comb += reset_signals.eq(Signal(6, reset=0b111111))
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gpio_signals = platform.request("gpio")
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self.submodules.leds = GPIOOut(gpio_signals)
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self.add_csr("leds")
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# Additional I2C Ports ---------------------------------------------------------------------
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self.submodules.i2c0 = I2CMaster(platform.request("i2c", 0))
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self.submodules.i2c1 = I2CMaster(platform.request("i2c", 1))
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self.submodules.i2c2 = I2CMaster(platform.request("i2c", 2))
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# JTAG -------------------------------------------------------------------------------------
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#self.add_jtagbone()
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# Backlight --------------------------------------------------------------------------------
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# Motherboard display connector backlight, currently unused (the new backlight signals
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# are on the 50pin RGB->eDP connector)
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backlight = platform.request("backlight")
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self.comb += backlight.en.eq(Signal(reset=1))
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self.comb += backlight.pwm.eq(Signal(reset=1))
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# eDP --------------------------------------------------------------------------------------
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self.submodules.videophy = VideoDVIPHY(platform.request("edp"), clock_domain="dvi")
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self.add_video_framebuffer(phy=self.videophy, timings="1920x1080@rkx7", clock_domain="dvi")
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# HDMI -------------------------------------------------------------------------------------
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# Untested: 2x VideoDVIPHYs and framebuffers in parallel
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#self.submodules.videophy = VideoDVIPHY(platform.request("hdmi"), clock_domain="dvi")
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# USB Host ---------------------------------------------------------------------------------
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self.submodules.usb_ohci = USBOHCI(platform, platform.request("usb"))
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self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False))
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self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma)
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self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt)
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# LiteScope UART
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self.add_uartbone(name="litescope_serial")
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# LiteScope Analyzer (optional)
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# analyzer_signals = [
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# ulpi_data.din,
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# utmi.linestate,
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# utmi.txvalid,
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# utmi.rxerror,
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# utmi.rxvalid,
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# usb_ulpi.dir,
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# usb_ulpi.stp,
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# usb_ulpi.nxt,
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# usbh_dbg_state,
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# ulpi_dbg_state,
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# usb_host_intr,
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# usb_host_dbg_intr,
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# ]
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# from litescope import LiteScopeAnalyzer
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# self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
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# depth = 256,
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# clock_domain = "ulpi",
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# csr_csv = "analyzer.csv")
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# Build --------------------------------------------------------------------------------------------
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@ -96,12 +186,12 @@ def main():
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
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target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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target_group.add_argument("--with-spi-flash", default=True, action="store_true", help="Enable SPI Flash (MMAPed).")
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sdopts = target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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sdopts.add_argument("--with-sdcard", default=True, action="store_true", help="Enable SDCard support.")
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ethopts = target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-ethernet", default=True, action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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builder_args(parser)
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soc_core_args(parser)
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@ -118,6 +208,9 @@ def main():
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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args.csr_csv="csr.csv"
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builder = Builder(soc, **builder_argdict(args))
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if args.build:
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builder.build()
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