mirror of
https://github.com/litex-hub/litex-boards.git
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Add embedfire_rise_pro
Add Flash
This commit is contained in:
Yu-Ti Kuo
parent
041c1607ce
commit
d7f2b5a929
2 changed files with 356 additions and 0 deletions
152
litex_boards/platforms/embedfire_rise_pro.py
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152
litex_boards/platforms/embedfire_rise_pro.py
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2024 Yu-Ti Kuo <bobgash2@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# embedfire rise pro FPGA: https://detail.tmall.com/item.htm?id=645153441975
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openocd import OpenOCD
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from litex.build.xilinx.programmer import VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk50" , 0, Pins("W19"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("N15"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("M21"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("L21"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("K21"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("K22"), IOStandard("LVCMOS33")),
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# Buttons
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("user_sw", 0, Pins("V17"), IOStandard("LVCMOS33")),
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("user_sw", 1, Pins("W17"), IOStandard("LVCMOS33")),
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("user_sw", 2, Pins("AA18"), IOStandard("LVCMOS33")),
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("user_sw", 3, Pins("AB18"), IOStandard("LVCMOS33")),
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# Beeper (Buzzer)
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("beeper", 0, Pins("M17"), IOStandard("LVCMOS33")),
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# Fan
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("fan", 0, Pins("W22"), IOStandard("LVCMOS33")),
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# Serial CH340G
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("serial", 0,
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Subsignal("tx", Pins("N17")),
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Subsignal("rx", Pins("P17")),
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IOStandard("LVCMOS33")
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),
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# I2C EEPROM 24C64
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("i2c", 0,
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Subsignal("scl", Pins("E22")),
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Subsignal("sda", Pins("D22")),
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IOStandard("LVCMOS33"),
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),
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# DDR3 SDRAM MT41K256M16
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("ddram", 0,
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Subsignal("a", Pins(
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"AA4 AB2 AA5 AB3 AB1 U2 W1 R2",
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"V2 U3 Y1 W2 Y2 U1 V3"),
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IOStandard("SSTL135")),
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Subsignal("ba", Pins("AA1 Y3 AA3"), IOStandard("SSTL135")),
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Subsignal("ras_n", Pins("W6"), IOStandard("SSTL135")),
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Subsignal("cas_n", Pins("U5"), IOStandard("SSTL135")),
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Subsignal("we_n", Pins("Y4"), IOStandard("SSTL135")),
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Subsignal("cs_n", Pins("T1"), IOStandard("SSTL135")),
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Subsignal("dm", Pins("D2 G2 M2 M5"), IOStandard("SSTL135")),
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Subsignal("dq", Pins(
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"C2 G1 A1 F3 B2 F1 B1 E2",
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"H3 G3 H2 H5 J1 J5 K1 H4",
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"L4 M3 L3 J6 K3 K6 J4 L5",
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"P1 N4 R1 N2 M6 N5 P6 P2"),
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IOStandard("SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins("E1 K2 M1 P5"),
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IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_n", Pins("D1 J2 L1 P4"),
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IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("clk_p", Pins("V4"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_n", Pins("W4"), IOStandard("DIFF_SSTL135")),
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Subsignal("cke", Pins("AB5"), IOStandard("SSTL135")),
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Subsignal("odt", Pins("T5"), IOStandard("SSTL135")),
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Subsignal("reset_n", Pins("R3"), IOStandard("SSTL135")),
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Misc("SLEW=FAST"),
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),
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# RGMII Ethernet (RTL8211F)
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("eth_clocks", 0,
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Subsignal("tx", Pins("C18")),
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Subsignal("rx", Pins("C19")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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#SubSignal("inib"), Pins("D21")),
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#Subsignal("rst_n", Pins("E21")),
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Subsignal("mdio", Pins("G22")),
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Subsignal("mdc", Pins("G21")),
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Subsignal("rx_ctl", Pins("C22")),
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Subsignal("rx_data", Pins("D20 C20 A18 A19")),
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Subsignal("tx_ctl", Pins("B22")),
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Subsignal("tx_data", Pins("B20 A20 B21 A21")),
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IOStandard("LVCMOS33")
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),
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# SDCard
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("spisdcard", 0,
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Subsignal("cd", Pins("AA19")),
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Subsignal("clk", Pins("Y22")),
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Subsignal("mosi", Pins("Y21")),
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Subsignal("cs_n", Pins("A14")),
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Subsignal("miso", Pins("AB21")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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("sdcard", 0,
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Subsignal("data", Pins("AB21 AB22 AB20 W21"),),
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Subsignal("cmd", Pins("Y21"),),
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Subsignal("clk", Pins("Y22")),
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Subsignal("cd", Pins("AA19")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [] # ToDo
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self, variant="a7-35", toolchain="vivado"):
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device = {
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"a7-35": "xc7a35tfgg484-2",
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"a7-100": "xc7a100tfgg484-2",
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"a7-200": "xc7a200tfbg484-2"
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}[variant]
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Xilinx7SeriesPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
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def create_programmer(self):
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return VivadoProgrammer(flash_part="mt25ql128-spi-x1_x2_x4")
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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204
litex_boards/targets/embedfire_rise_pro.py
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204
litex_boards/targets/embedfire_rise_pro.py
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2024 Yu-Ti Kuo <bobgash2@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# embedfire rise pro FPGA: https://detail.tmall.com/item.htm?id=645153441975
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import embedfire_rise_pro
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.gpio import GPIOIn
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from litex.soc.cores.xadc import XADC
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from litex.soc.cores.dna import DNA
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from litex.soc.cores.pwm import PWM
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from litedram.modules import MT41K256M16
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from litedram.phy import s7ddrphy
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from liteeth.phy.mii import LiteEthPHYMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_dram=True, with_rst=True):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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if with_dram:
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self.cd_sys4x = ClockDomain()
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self.cd_sys4x_dqs = ClockDomain()
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self.cd_idelay = ClockDomain()
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# # #
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# Clk/Rst.
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clk50 = platform.request("clk50")
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rst = ~platform.request("cpu_reset") if with_rst else 0
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# PLL.
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self.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(rst | self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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if with_dram:
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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# IdelayCtrl.
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if with_dram:
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self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=50e6,
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with_xadc = False,
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with_dna = False,
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with_ethernet = False,
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with_etherbone = False,
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eth_ip = "192.168.1.50",
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remote_ip = None,
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eth_dynamic_ip = False,
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with_led_chaser = True,
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with_buttons = False,
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with_beeper = True,
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**kwargs):
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platform = embedfire_rise_pro.Platform(variant=variant, toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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with_dram = (kwargs.get("integrated_main_ram_size", 0) == 0)
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self.crg = _CRG(platform, sys_clk_freq, with_dram)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on embedfire", **kwargs)
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# XADC -------------------------------------------------------------------------------------
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if with_xadc:
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self.xadc = XADC()
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# DNA --------------------------------------------------------------------------------------
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if with_dna:
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self.dna = DNA()
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self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K256M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.ethphy = LiteEthPHYMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip, with_ethmac=with_ethernet)
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elif with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip, local_ip=eth_ip, remote_ip=remote_ip)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq,
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)
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self.leds.add_pwm()
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# Buttons ----------------------------------------------------------------------------------
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if with_buttons:
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self.buttons = GPIOIn(
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pads = platform.request_all("user_btn"),
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with_irq = self.irq.enabled
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)
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# Beeper------------------------------------------------------------------------------------
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self.beeper = PWM(
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pwm=platform.request("beeper", 0),
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with_csr = True,
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default_enable = False,
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default_width = 0x800,
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default_period = 0xfff,
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)
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self.fan_pwm = PWM(
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pwm=platform.request("fan", 0),
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with_csr = True,
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default_enable = False,
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default_width = 0x800,
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default_period = 0xfff,
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)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=embedfire_rise_pro.Platform, description="LiteX SoC on embedfire rise pro.")
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parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
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parser.add_target_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100 or a7-200).")
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parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-xadc", action="store_true", help="Enable 7-Series XADC.")
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parser.add_target_argument("--with-dna", action="store_true", help="Enable 7-Series DNA.")
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parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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parser.add_target_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
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parser.add_target_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server.")
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parser.add_target_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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sdopts = parser.target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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args = parser.parse_args()
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assert not (args.with_etherbone and args.eth_dynamic_ip)
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soc = BaseSoC(
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variant = args.variant,
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toolchain = args.toolchain,
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sys_clk_freq = args.sys_clk_freq,
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with_xadc = args.with_xadc,
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with_dna = args.with_dna,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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remote_ip = args.remote_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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**parser.soc_argdict
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)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, builder.get_bitstream_filename(mode="flash"))
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if __name__ == "__main__":
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main()
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