Merge pull request #507 from hansfbaier/master
sitlinv_stlv7325_v2: VCCIO jumper default factory setting is 3.3V
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commit
d874d344d2
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@ -486,13 +486,14 @@ class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk200"
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default_clk_period = 1e9/200e6
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def __init__(self, vccio="2.5V"):
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def __init__(self, vccio):
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assert vccio in ["2.5V", "3.3V"]
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Xilinx7SeriesPlatform.__init__(self, "xc7k325t-ffg676-2", _get_io(vccio), _connectors, toolchain="vivado")
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self.add_platform_command("""
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 2.5 [current_design]
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set_property CONFIG_VOLTAGE %s [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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""")
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""" % vccio.replace("V", ""))
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self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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@ -72,7 +72,7 @@ class _CRG(LiteXModule):
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=100e6,
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vccio = "2.5V",
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vccio = "3.3V",
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with_ethernet = False,
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with_led_chaser = True,
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with_pcie = False,
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@ -172,7 +172,7 @@ def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=sitlinv_stlv7325_v2.Platform, description="LiteX SoC on AliExpress STLV7325-v2.")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--vccio", default="2.5V", type=str, help="IO Voltage (set by J4), can be 2.5V or 3.3V")
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parser.add_target_argument("--vccio", default="3.3V", type=str, help="IO Voltage (set by J4), can be 2.5V or 3.3V")
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parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
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parser.add_target_argument("--driver", action="store_true", help="Generate PCIe driver.")
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parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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