Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #507 from hansfbaier/master 

sitlinv_stlv7325_v2: VCCIO jumper default factory setting is 3.3V
This commit is contained in:
enjoy-digital 2023-06-07 14:08:14 +02:00 committed by GitHub
parent b01abce7d5 765ee1a3ce
commit d874d344d2
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 6 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
litex_boards/platforms/sitlinv_stlv7325_v2.py
View File

@ -486,13 +486,14 @@ class Platform(Xilinx7SeriesPlatform):
default_clk_name = "clk200" default_clk_name = "clk200"
default_clk_period = 1e9/200e6 default_clk_period = 1e9/200e6
def __init__(self, vccio="2.5V"): def __init__(self, vccio):
assert vccio in ["2.5V", "3.3V"]
Xilinx7SeriesPlatform.__init__(self, "xc7k325t-ffg676-2", _get_io(vccio), _connectors, toolchain="vivado") Xilinx7SeriesPlatform.__init__(self, "xc7k325t-ffg676-2", _get_io(vccio), _connectors, toolchain="vivado")
self.add_platform_command(""" self.add_platform_command("""
set_property CFGBVS VCCO [current_design] set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 2.5 [current_design] set_property CONFIG_VOLTAGE %s [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
""") """ % vccio.replace("V", ""))
self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]

4
litex_boards/targets/sitlinv_stlv7325_v2.py
View File

@ -72,7 +72,7 @@ class _CRG(LiteXModule):
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=100e6, def __init__(self, sys_clk_freq=100e6,
vccio = "2.5V", vccio = "3.3V",
with_ethernet = False, with_ethernet = False,
with_led_chaser = True, with_led_chaser = True,
with_pcie = False, with_pcie = False,
@ -172,7 +172,7 @@ def main():
from litex.build.parser import LiteXArgumentParser from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=sitlinv_stlv7325_v2.Platform, description="LiteX SoC on AliExpress STLV7325-v2.") parser = LiteXArgumentParser(platform=sitlinv_stlv7325_v2.Platform, description="LiteX SoC on AliExpress STLV7325-v2.")
parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.") parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
parser.add_target_argument("--vccio", default="2.5V", type=str, help="IO Voltage (set by J4), can be 2.5V or 3.3V") parser.add_target_argument("--vccio", default="3.3V", type=str, help="IO Voltage (set by J4), can be 2.5V or 3.3V")
parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.") parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
parser.add_target_argument("--driver", action="store_true", help="Generate PCIe driver.") parser.add_target_argument("--driver", action="store_true", help="Generate PCIe driver.")
parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")