zcu104: add separate ddram_32/64 definitions and use ddram_32 for now.
Ease switching between ddram_32 and ddram_64.
This commit is contained in:
Florent Kermarrec
parent
8ecfb13f3c
commit
d87b8b3c66
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@ -43,50 +43,74 @@ _io = [
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IOStandard("LVCMOS18")
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),
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("ddram", 0,
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Subsignal("a", Pins(
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("ddram_32", 0,
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Subsignal("a", Pins(
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"AH16 AG14 AG15 AF15 AF16 AJ14 AH14 AF17",
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"AK17 AJ17 AK14 AK15 AL18 AK18"),
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IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("AL15 AL16"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("AC16 AB16"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("AD15"), IOStandard("SSTL12_DCI")), # A16
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Subsignal("cas_n", Pins("AA14"), IOStandard("SSTL12_DCI")), # A15
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Subsignal("we_n", Pins("AA16"), IOStandard("SSTL12_DCI")), # A14
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Subsignal("cs_n", Pins("AA15"), IOStandard("SSTL12_DCI")), # also AL17 AN17 AN16 for larger SODIMMs
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Subsignal("act_n", Pins("AC17"), IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("AL15 AL16"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("AC16 AB16"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("AD15"), IOStandard("SSTL12_DCI")), # A16
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Subsignal("cas_n", Pins("AA14"), IOStandard("SSTL12_DCI")), # A15
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Subsignal("we_n", Pins("AA16"), IOStandard("SSTL12_DCI")), # A14
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Subsignal("cs_n", Pins("AA15"), IOStandard("SSTL12_DCI")), # also AL17 AN17 AN16 for larger SODIMMs
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Subsignal("act_n", Pins("AC17"), IOStandard("SSTL12_DCI")),
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#Subsignal("alert_n", Pins("AB15"), IOStandard("SSTL12_DCI")),
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#Subsignal("par", Pins("AD16"), IOStandard("SSTL12_DCI")),
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#FIXME: Use full bus width
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#Subsignal("dm", Pins("AH22 AE18 AL20 AP19 AF11 AH12 AK13 AN12"),
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Subsignal("dm", Pins("AF11 AH12 AK13 AN12"),
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#Subsignal("par", Pins("AD16"), IOStandard("SSTL12_DCI")),
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Subsignal("dm", Pins("AF11 AH12 AK13 AN12"),
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IOStandard("POD12_DCI")),
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Subsignal("dq", Pins(
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# "AE24 AE23 AF22 AF21 AG20 AG19 AH21 AG21",
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# "AA20 AA19 AD19 AC18 AE20 AD20 AC19 AB19",
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# "AJ22 AJ21 AK20 AJ20 AK19 AJ19 AL23 AL22",
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# "AN23 AM23 AP23 AN22 AP22 AP21 AN19 AM19",
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Subsignal("dq", Pins(
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"AC13 AB13 AF12 AE12 AF13 AE13 AE14 AD14",
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"AG8 AF8 AG10 AG11 AH13 AG13 AJ11 AH11",
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"AK9 AJ9 AK10 AJ10 AL12 AK12 AL10 AL11",
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"AM8 AM9 AM10 AM11 AP11 AN11 AP9 AP10"),
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IOStandard("POD12_DCI")),
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Subsignal("dqs_p", Pins("AC12 AG9 AK8 AN9"),
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IOStandard("DIFF_POD12_DCI")),
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Subsignal("dqs_n", Pins("AD12 AH9 AL8 AN8"),
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IOStandard("DIFF_POD12_DCI")),
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Subsignal("clk_p", Pins("AF18"), IOStandard("DIFF_SSTL12_DCI")), # also AJ16 for larger SODIMMs
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Subsignal("clk_n", Pins("AG18"), IOStandard("DIFF_SSTL12_DCI")), # also AJ15 for larger SODIMMs
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Subsignal("cke", Pins("AD17"), IOStandard("SSTL12_DCI")), # also AM15 for larger SODIMMs
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Subsignal("odt", Pins("AE15"), IOStandard("SSTL12_DCI")), # also AM16 for larger SODIMMs
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Subsignal("reset_n", Pins("AB14"), IOStandard("LVCMOS12")),
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Misc("SLEW=FAST"),
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),
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("ddram_64", 0, # FIXME: not yet working
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Subsignal("a", Pins(
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"AH16 AG14 AG15 AF15 AF16 AJ14 AH14 AF17",
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"AK17 AJ17 AK14 AK15 AL18 AK18"),
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IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("AL15 AL16"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("AC16 AB16"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("AD15"), IOStandard("SSTL12_DCI")), # A16
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Subsignal("cas_n", Pins("AA14"), IOStandard("SSTL12_DCI")), # A15
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Subsignal("we_n", Pins("AA16"), IOStandard("SSTL12_DCI")), # A14
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Subsignal("cs_n", Pins("AA15"), IOStandard("SSTL12_DCI")), # also AL17 AN17 AN16 for larger SODIMMs
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Subsignal("act_n", Pins("AC17"), IOStandard("SSTL12_DCI")),
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#Subsignal("alert_n", Pins("AB15"), IOStandard("SSTL12_DCI")),
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#Subsignal("par", Pins("AD16"), IOStandard("SSTL12_DCI")),
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Subsignal("dm", Pins("AH22 AE18 AL20 AP19 AF11 AH12 AK13 AN12"),
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IOStandard("POD12_DCI")),
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Subsignal("dq", Pins(
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"AE24 AE23 AF22 AF21 AG20 AG19 AH21 AG21",
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"AA20 AA19 AD19 AC18 AE20 AD20 AC19 AB19",
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"AJ22 AJ21 AK20 AJ20 AK19 AJ19 AL23 AL22",
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"AN23 AM23 AP23 AN22 AP22 AP21 AN19 AM19",
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"AC13 AB13 AF12 AE12 AF13 AE13 AE14 AD14",
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"AG8 AF8 AG10 AG11 AH13 AG13 AJ11 AH11",
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"AK9 AJ9 AK10 AJ10 AL12 AK12 AL10 AL11",
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"AM8 AM9 AM10 AM11 AP11 AN11 AP9 AP10"
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),
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"AM8 AM9 AM10 AM11 AP11 AN11 AP9 AP10"),
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IOStandard("POD12_DCI")),
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#Subsignal("dqs_p", Pins("AF23 AA18 AK22 AM21 AC12 AG9 AK8 AN9"),
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# IOStandard("DIFF_POD12_DCI")),
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Subsignal("dqs_p", Pins("AC12 AG9 AK8 AN9"),
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Subsignal("dqs_p", Pins("AF23 AA18 AK22 AM21 AC12 AG9 AK8 AN9"),
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IOStandard("DIFF_POD12_DCI")),
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#Subsignal("dqs_n", Pins("AG23 AB18 AK23 AN21 AD12 AH9 AL8 AN8"),
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# IOStandard("DIFF_POD12_DCI")),
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Subsignal("dqs_n", Pins("AD12 AH9 AL8 AN8"),
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Subsignal("dqs_n", Pins("AG23 AB18 AK23 AN21 AD12 AH9 AL8 AN8"),
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IOStandard("DIFF_POD12_DCI")),
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Subsignal("clk_p", Pins("AF18"), IOStandard("DIFF_SSTL12_DCI")), # also AJ16 for larger SODIMMs
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Subsignal("clk_n", Pins("AG18"), IOStandard("DIFF_SSTL12_DCI")), # also AJ15 for larger SODIMMs
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Subsignal("cke", Pins("AD17"), IOStandard("SSTL12_DCI")), # also AM15 for larger SODIMMs
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Subsignal("odt", Pins("AE15"), IOStandard("SSTL12_DCI")), # also AM16 for larger SODIMMs
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Subsignal("clk_p", Pins("AF18"), IOStandard("DIFF_SSTL12_DCI")), # also AJ16 for larger SODIMMs
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Subsignal("clk_n", Pins("AG18"), IOStandard("DIFF_SSTL12_DCI")), # also AJ15 for larger SODIMMs
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Subsignal("cke", Pins("AD17"), IOStandard("SSTL12_DCI")), # also AM15 for larger SODIMMs
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Subsignal("odt", Pins("AE15"), IOStandard("SSTL12_DCI")), # also AM16 for larger SODIMMs
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Subsignal("reset_n", Pins("AB14"), IOStandard("LVCMOS12")),
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Misc("SLEW=FAST"),
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),
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@ -95,7 +119,7 @@ _io = [
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk125"
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default_clk_name = "clk125"
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default_clk_period = 1e9/125e6
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def __init__(self):
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@ -85,7 +85,7 @@ class BaseSoC(SoCSDRAM):
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# DDR4 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
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self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram_32"), # FIXME: use ddram_64
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memtype = "DDR4",
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sim_device = "ULTRASCALE_PLUS",
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iodelay_clk_freq = 500e6,
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