digilent_arty: Add --flash support.
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4894926c40
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@ -134,6 +134,7 @@ def main():
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parser.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado, symbiflow or yosys+nextpnr).")
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parser.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado, symbiflow or yosys+nextpnr).")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--flash", action="store_true", help="Flash bitstream.")
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parser.add_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).")
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parser.add_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
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ethopts = parser.add_mutually_exclusive_group()
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ethopts = parser.add_mutually_exclusive_group()
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@ -185,5 +186,9 @@ def main():
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prog = soc.platform.create_programmer()
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, os.path.join(builder.gateware_dir, soc.build_name + ".bin"))
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if __name__ == "__main__":
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if __name__ == "__main__":
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main()
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main()
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