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efinix_trion_t20_bga256_dev_kit: Cleanup/Review platform/target.

This commit is contained in:
Florent Kermarrec 2024-06-19 08:23:43 +02:00
parent 8eaa4d637e
commit dad6b2b9b6
2 changed files with 30 additions and 31 deletions
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14
litex_boards/platforms/efinix_trion_t20_bga256_dev_kit.py
View File

@ -11,17 +11,17 @@ from litex.build.efinix import EfinixProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk
# Clk.
("clk50", 0, Pins("L13"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
# Serial
# Serial.
("serial", 0,
Subsignal("tx", Pins("H4:18")), # 27 on H4
Subsignal("rx", Pins("H4:19")), # 28 on H4
IOStandard("3.3_V_LVTTL_/_LVCMOS") , Misc("WEAK_PULLUP")
),
# Leds
# Leds.
("user_led", 0, Pins("D14"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
("user_led", 1, Pins("E13"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
("user_led", 2, Pins("G13"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
@ -31,17 +31,17 @@ _io = [
("user_led", 6, Pins("P15"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
("user_led", 7, Pins("M14"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
# Buttons
# Buttons.
("user_btn", 0, Pins("P2"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
("user_btn", 1, Pins("N3"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
("user_btn", 2, Pins("L4"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
# Switches
# Switches.
("user_sw", 0, Pins("H14"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
("user_sw", 1, Pins("H15"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
("user_sw", 2, Pins("H16"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
# SPIFlash
# SPIFlash.
("spiflash", 0,
Subsignal("cs_n", Pins("P3")),
Subsignal("clk", Pins("M3")),
@ -50,7 +50,7 @@ _io = [
IOStandard("3.3_V_LVTTL_/_LVCMOS")
),
# SDRAM NDS36PT5-20ET
# SDRAM (NDS36PT5-20ET).
("sdram_clock", 0, Pins("P16"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("SLEW=FAST")),
("sdram", 0,
Subsignal("a", Pins("C12 D11 C11 E11 J13 J14 J15 K12 K14 L15 D12 L16 M12")),

9
litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py
View File

@ -29,8 +29,6 @@ from litedram.phy import GENSDRPHY
# CRG ----------------------------------------------------------------------------------------------
class _CRG(LiteXModule):
name_sdram_clk = "sdram_clk"
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.cd_sys = ClockDomain()
@ -38,15 +36,16 @@ class _CRG(LiteXModule):
# # #
# Clk/Rst.
clk50 = platform.request("clk50")
rst_n = platform.request("user_btn", 0)
# PLL
# PLL.
self.pll = pll = TRIONPLL(platform)
self.comb += pll.reset.eq(~rst_n | self.rst)
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180, name=self.name_sdram_clk)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180, name="sdram_clk")
# BaseSoC ------------------------------------------------------------------------------------------
@ -62,7 +61,7 @@ class BaseSoC(SoCCore):
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size and sys_clk_freq <= 50e6 :
self.specials += ClkOutput(self.crg.name_sdram_clk, platform.request("sdram_clock"))
self.specials += ClkOutput("sdram_clk", platform.request("sdram_clock"))
self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",