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targets/de10lite: use Max10PLL, remove 50MHz limitation.

This commit is contained in:
Florent Kermarrec 2020-04-08 08:55:30 +02:00
parent 9fe982150c
commit db67dff0ea
1 changed files with 8 additions and 41 deletions
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49
litex_boards/targets/de10lite.py
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@ -10,6 +10,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import de10lite
from litex.soc.cores.clock import Max10PLL
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
@ -22,7 +23,7 @@ from litevideo.terminal.core import Terminal
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
self.clock_domains.cd_vga = ClockDomain(reset_less=True)
@ -34,44 +35,11 @@ class _CRG(Module):
platform.add_period_constraint(clk50, 1e9/50e6)
# PLL
pll_locked = Signal()
pll_clk_out = Signal(6)
self.specials += \
Instance("ALTPLL",
p_BANDWIDTH_TYPE = "AUTO",
p_CLK0_DIVIDE_BY = 1,
p_CLK0_DUTY_CYCLE = 50,
p_CLK0_MULTIPLY_BY = 1,
p_CLK0_PHASE_SHIFT = "0",
p_CLK1_DIVIDE_BY = 1,
p_CLK1_DUTY_CYCLE = 50,
p_CLK1_MULTIPLY_BY = 1,
p_CLK1_PHASE_SHIFT = "5000", # 90°
p_CLK2_DIVIDE_BY = 2,
p_CLK2_DUTY_CYCLE = 50,
p_CLK2_MULTIPLY_BY = 1,
p_CLK2_PHASE_SHIFT = "0",
p_COMPENSATE_CLOCK = "CLK0",
p_INCLK0_INPUT_FREQUENCY = 20000,
p_OPERATION_MODE = "NORMAL",
i_INCLK = clk50,
o_CLK = pll_clk_out,
i_CLKENA = 0x3f,
i_EXTCLKENA = 0xf,
i_FBIN = 1,
i_PFDENA = 1,
i_PLLENA = 1,
o_LOCKED = pll_locked,
)
self.comb += [
self.cd_sys.clk.eq(pll_clk_out[0]),
self.cd_sys_ps.clk.eq(pll_clk_out[1]),
self.cd_vga.clk.eq(pll_clk_out[2])
]
self.specials += [
AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
AsyncResetSynchronizer(self.cd_vga, ~pll_locked),
]
self.submodules.pll = pll = Max10PLL(speedgrade="-7")
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
pll.create_clkout(self.cd_vga, 25e6)
# SDRAM clock
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
@ -80,14 +48,13 @@ class _CRG(Module):
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = de10lite.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size: