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Add tweaks to Arty board to support yosys+nextpnr toolchain

This commit is contained in:
Victor Suarez Rovere 2022-01-24 02:06:34 -03:00
parent 787f44e7d9
commit db77ea5c7a
2 changed files with 14 additions and 6 deletions
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7
litex_boards/platforms/digilent_arty.py
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@ -295,7 +295,7 @@ def sdcard_pmod_io(pmod):
Subsignal("mosi", Pins(f"{pmod}:1"), Misc("PULLUP True")),
Subsignal("cs_n", Pins(f"{pmod}:0"), Misc("PULLUP True")),
Subsignal("miso", Pins(f"{pmod}:2"), Misc("PULLUP True")),
Misc("SLEW=FAST"),
Misc("SLEW=FAST"), #NOTE: this is not supported by yosys+nextprn toolchain
IOStandard("LVCMOS33"),
),
("sdcard", 0,
@ -303,7 +303,7 @@ def sdcard_pmod_io(pmod):
Subsignal("cmd", Pins(f"{pmod}:1"), Misc("PULLUP True")),
Subsignal("clk", Pins(f"{pmod}:3")),
Subsignal("cd", Pins(f"{pmod}:6")),
Misc("SLEW=FAST"),
Misc("SLEW=FAST"), #NOTE: this and all Misc() is not supported by yosys+nextprn toolchain
IOStandard("LVCMOS33"),
),
]
@ -349,7 +349,8 @@ class Platform(XilinxPlatform):
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
if toolchain != "yosys+nextpnr": #this is not supported by yosys+pnr
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
def create_programmer(self):
bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"

13
litex_boards/targets/digilent_arty.py
View File

@ -5,8 +5,14 @@
#
# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# Copyright (c) 2022 Victor Suarez Rovere <suarezvictor@gmail.com>
# SPDX-License-Identifier: BSD-2-Clause
#NOTE: for yosys+nextpnr toolchain DDR3 should be disabled
#and max frequency should be according to CPU.
#Example:
#./digilent_arty.py --sys-clk-freq=50e6 --integrated-main-ram-size=8192 --cpu-type=femtorv --toolchain=yosys+nextpnr --build
import os
import argparse
@ -30,7 +36,7 @@ from liteeth.phy.mii import LiteEthPHYMII
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq, with_rst=True):
def __init__(self, platform, sys_clk_freq, with_rst=True, use_delayctrl=True):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
@ -53,7 +59,8 @@ class _CRG(Module):
pll.create_clkout(self.cd_eth, 25e6)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
if use_delayctrl: #should be skipped for yosys+nextpnr
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
@ -72,7 +79,7 @@ class BaseSoC(SoCCore):
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.submodules.crg = _CRG(platform, sys_clk_freq, use_delayctrl = (toolchain != "yosys+nextpnr"))
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size: