Merge pull request #56 from rob-ng15/master
de10nano add in support for MiSTer secondary sd card
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commit
db9d5489ec
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@ -101,6 +101,15 @@ _mister_sdram_module_io = [
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Subsignal("we_n", Pins("AA19")),
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Subsignal("we_n", Pins("AA19")),
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IOStandard("3.3-V LVTTL")
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IOStandard("3.3-V LVTTL")
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),
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),
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# SPI SD CARD HARDWARE BITBANGING
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("spi",0,
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Subsignal("clk", Pins("AH26")),
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Subsignal("mosi", Pins("AF27")),
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Subsignal("cs_n", Pins("AF28")),
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Subsignal("miso", Pins("AF25")),
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IOStandard("3.3-V LVTTL")
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),
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]
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]
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# Platform -----------------------------------------------------------------------------------------
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# Platform -----------------------------------------------------------------------------------------
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@ -17,6 +17,9 @@ from litex.soc.integration.builder import *
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from litedram.modules import AS4C16M16
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from litedram.modules import AS4C16M16
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from litedram.phy import GENSDRPHY
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from litedram.phy import GENSDRPHY
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#SPI SD CARD HARDWARE BITBANGING
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from litex.soc.cores.spi import SPIMaster
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# CRG ----------------------------------------------------------------------------------------------
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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class _CRG(Module):
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@ -103,6 +106,12 @@ class MiSTerSDRAMSoC(SoCSDRAM):
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geom_settings = sdram_module.geom_settings,
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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timing_settings = sdram_module.timing_settings)
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# SPI SDCARD HARDWARE BITBANGING
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spi_pads = self.platform.request("spi")
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self.add_csr("spi")
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spi_clk_freq = 400e3
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self.submodules.spi = SPIMaster(spi_pads, 8, sys_clk_freq, spi_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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# Build --------------------------------------------------------------------------------------------
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def main():
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def main():
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