Merge pull request #56 from rob-ng15/master

de10nano add in support for MiSTer secondary sd card
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enjoy-digital 2020-03-19 11:07:40 +01:00 committed by GitHub
commit db9d5489ec
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2 changed files with 18 additions and 0 deletions

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@ -101,6 +101,15 @@ _mister_sdram_module_io = [
Subsignal("we_n", Pins("AA19")), Subsignal("we_n", Pins("AA19")),
IOStandard("3.3-V LVTTL") IOStandard("3.3-V LVTTL")
), ),
# SPI SD CARD HARDWARE BITBANGING
("spi",0,
Subsignal("clk", Pins("AH26")),
Subsignal("mosi", Pins("AF27")),
Subsignal("cs_n", Pins("AF28")),
Subsignal("miso", Pins("AF25")),
IOStandard("3.3-V LVTTL")
),
] ]
# Platform ----------------------------------------------------------------------------------------- # Platform -----------------------------------------------------------------------------------------

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@ -17,6 +17,9 @@ from litex.soc.integration.builder import *
from litedram.modules import AS4C16M16 from litedram.modules import AS4C16M16
from litedram.phy import GENSDRPHY from litedram.phy import GENSDRPHY
#SPI SD CARD HARDWARE BITBANGING
from litex.soc.cores.spi import SPIMaster
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
class _CRG(Module): class _CRG(Module):
@ -103,6 +106,12 @@ class MiSTerSDRAMSoC(SoCSDRAM):
geom_settings = sdram_module.geom_settings, geom_settings = sdram_module.geom_settings,
timing_settings = sdram_module.timing_settings) timing_settings = sdram_module.timing_settings)
# SPI SDCARD HARDWARE BITBANGING
spi_pads = self.platform.request("spi")
self.add_csr("spi")
spi_clk_freq = 400e3
self.submodules.spi = SPIMaster(spi_pads, 8, sys_clk_freq, spi_clk_freq)
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------
def main(): def main():