Merge pull request #52 from antmicro/jboc/mercury-xu5
add Enclustra Mercury XU5 board
This commit is contained in:
enjoy-digital
GitHub
commit
dc1371108d
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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('clk100', 0,
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Subsignal('n', Pins('AD4'), IOStandard('DIFF_SSTL12_DCI')),
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Subsignal('p', Pins('AD5'), IOStandard('DIFF_SSTL12_DCI')),
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),
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('clk100_gtr', 0,
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Subsignal('p', Pins('C21'), IOStandard('DIFF_SSTL12')),
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Subsignal('n', Pins('C22'), IOStandard('DIFF_SSTL12')),
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),
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('clk27_gtr', 0,
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Subsignal('p', Pins('A21'), IOStandard('DIFF_SSTL12')),
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Subsignal('n', Pins('A22'), IOStandard('DIFF_SSTL12')),
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),
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('clk33', 0, Pins('AD4'), IOStandard('SSTL12')),
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('cpu_reset', 0, Pins('N19'), IOStandard('LVCMOS33')),
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('user_led', 0, Pins('H2'), IOStandard('LVCMOS18')),
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('user_led', 1, Pins('P9'), IOStandard('LVCMOS18')),
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('user_led', 2, Pins('K5'), IOStandard('LVCMOS18')),
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('serial', 0,
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Subsignal('rx', Pins('AA10')), # Module connector A: A60 (Meccury PE1: "IO B" connector 32)
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Subsignal('tx', Pins('AA11')), # Module connector A: A58 (Meccury PE1: "IO B" connector 31)
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IOStandard('LVCMOS33'),
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),
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('ddram', 0, # TODO: remove Misc with default settings
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Subsignal('a', Pins(
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'AC4 AC3 AB4 AB3 AB2 AC2 AB1 AC1',
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'AB5 AG4 AH4 AG3 AH3 AE3'), IOStandard('SSTL12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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),
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Subsignal('we_n', Pins('AF3'), IOStandard('SSTL12_DCI'), # A14
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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),
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Subsignal('cas_n', Pins('AE2'), IOStandard('SSTL12_DCI'), # A15
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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),
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Subsignal('ras_n', Pins('AF2'), IOStandard('SSTL12_DCI'), # A16
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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),
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Subsignal('ba', Pins('AH1 AF1'), IOStandard('SSTL12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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),
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# Subsignal('bg', Pins('AG1 AD9'), IOStandard('SSTL12_DCI'),
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Subsignal('bg', Pins('AG1'), IOStandard('SSTL12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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),
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Subsignal('cs_n', Pins('AH9'), IOStandard('SSTL12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=SDR'),
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),
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Subsignal('act_n', Pins('AH2'), IOStandard('SSTL12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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),
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Subsignal('dm', Pins('AC9 AG9'), IOStandard('POD12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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# Misc('EQUALIZATION=EQ_LEVEL2'),
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Misc('DATA_RATE=DDR'),
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),
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Subsignal('dq', Pins(
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'AB6 AC6 AE9 AE8 AB8 AC8 AB7 AC7',
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'AE5 AF5 AF8 AG8 AH8 AH7 AF7 AF6'), IOStandard('POD12_DCI'),
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Misc('PRE_EMPHASIS=RDRV_240'),
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Misc('EQUALIZATION=EQ_LEVEL2'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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Misc('ODT=RTT_40'),
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),
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Subsignal('dqs_p', Pins('AD7 AG6'), IOStandard('DIFF_POD12_DCI'),
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Misc('PRE_EMPHASIS=RDRV_240'),
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Misc('EQUALIZATION=EQ_LEVEL2'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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Misc('ODT=RTT_40'),
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),
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Subsignal('dqs_n', Pins('AE7 AG5'), IOStandard('DIFF_POD12_DCI'),
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Misc('PRE_EMPHASIS=RDRV_240'),
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Misc('EQUALIZATION=EQ_LEVEL2'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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Misc('ODT=RTT_40'),
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),
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Subsignal('clk_p', Pins('AD2'), IOStandard('DIFF_SSTL12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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),
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Subsignal('clk_n', Pins('AD1'), IOStandard('DIFF_SSTL12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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),
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Subsignal('cke', Pins('AH6'), IOStandard('SSTL12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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),
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Subsignal('odt', Pins('AE4'), IOStandard('SSTL12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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),
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Subsignal('reset_n', Pins('G4'), IOStandard('LVCMOS18'),
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Misc('DRIVE=8'),
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),
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Misc('SLEW=FAST'),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = []
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = 'clk100'
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default_clk_period = 1e9/100e6
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def __init__(self):
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XilinxPlatform.__init__(self, 'xczu2eg-sfvc784-1-i', _io, _connectors, toolchain='vivado')
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_platform_command('set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]')
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self.add_platform_command('set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]')
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self.add_platform_command('set_property INTERNAL_VREF 0.600 [get_iobanks 64]')
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@ -0,0 +1,111 @@
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#!/usr/bin/env python3
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import argparse
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from migen import *
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from migen.genlib.io import CRG
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from litex_boards.platforms import mercury_xu5
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import MT40A256M16
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from litedram.phy import usddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk400 = ClockDomain()
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self.clock_domains.cd_ic = ClockDomain()
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self.submodules.pll = pll = USMMCM(speedgrade=-1)
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_clk400, 400e6, with_reset=False)
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self.specials += [
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Instance("BUFGCE_DIV", name="main_bufgce_div",
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p_BUFGCE_DIVIDE=4,
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
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Instance("BUFGCE", name="main_bufgce",
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
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AsyncResetSynchronizer(self.cd_clk400, ~pll.locked),
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]
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ic_reset_counter = Signal(max=64, reset=63)
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ic_reset = Signal(reset=1)
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self.sync.clk400 += \
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If(ic_reset_counter != 0,
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ic_reset_counter.eq(ic_reset_counter - 1)
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).Else(
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ic_reset.eq(0)
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)
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ic_rdy = Signal()
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ic_rdy_counter = Signal(max=64, reset=63)
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self.cd_sys.rst.reset = 1
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self.comb += self.cd_ic.clk.eq(self.cd_sys.clk)
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self.sync.ic += [
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If(ic_rdy,
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If(ic_rdy_counter != 0,
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ic_rdy_counter.eq(ic_rdy_counter - 1)
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).Else(
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self.cd_sys.rst.eq(0)
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)
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)
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]
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self.specials += [
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Instance("IDELAYCTRL", p_SIM_DEVICE="ULTRASCALE",
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i_REFCLK=ClockSignal("clk400"), i_RST=ic_reset,
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o_RDY=ic_rdy),
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AsyncResetSynchronizer(self.cd_ic, ic_reset)
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]
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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def __init__(self, sys_clk_freq=int(100e6), **kwargs):
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platform = mercury_xu5.Platform()
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR4 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
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memtype = "DDR4",
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sim_device = "ULTRASCALE_PLUS",
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iodelay_clk_freq = 400e6,
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cmd_latency = 1,
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sys_clk_freq = sys_clk_freq)
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self.add_csr("ddrphy")
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self.add_constant("USDDRPHY", None)
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sdram_module = MT40A256M16(sys_clk_freq, "1:4")
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self.register_sdram(self.ddrphy,
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Enclustra's Mercury XU5")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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