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Merge pull request #424 from slagernate/main 

add option to use ecpprog for crosslink-nx eval board
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enjoy-digital 2022-09-19 13:33:48 +02:00 committed by GitHub
parent 30180892fa 9dbee62eac
commit dcb9e2b763
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2 changed files with 15 additions and 4 deletions
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8
litex_boards/platforms/lattice_crosslink_nx_evn.py
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@ -8,6 +8,7 @@
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import LatticeProgrammer from litex.build.lattice.programmer import LatticeProgrammer
from litex.build.lattice.programmer import EcpprogProgrammer
# IOs ---------------------------------------------------------------------------------------------- # IOs ----------------------------------------------------------------------------------------------
@ -258,8 +259,13 @@ class Platform(LatticePlatform):
assert device in ["LIFCL-40-9BG400C", "LIFCL-40-8BG400CES"] assert device in ["LIFCL-40-9BG400C", "LIFCL-40-8BG400CES"]
LatticePlatform.__init__(self, device, _io, _connectors, toolchain=toolchain, **kwargs) LatticePlatform.__init__(self, device, _io, _connectors, toolchain=toolchain, **kwargs)
def create_programmer(self, mode = "direct"): def create_programmer(self, mode = "direct", prog="radiant"):
assert mode in ["direct","flash"] assert mode in ["direct","flash"]
assert prog in ["radiant","ecpprog"]
if prog == "ecpprog":
return EcpprogProgrammer()
xcf_template_direct = """<?xml version='1.0' encoding='utf-8' ?> xcf_template_direct = """<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" > <!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >

9
litex_boards/targets/lattice_crosslink_nx_evn.py
View File

@ -97,9 +97,11 @@ def main():
target_group.add_argument("--build", action="store_true", help="Build design.") target_group.add_argument("--build", action="store_true", help="Build design.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.") target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="radiant", help="FPGA toolchain (radiant or prjoxide).") target_group.add_argument("--toolchain", default="radiant", help="FPGA toolchain (radiant or prjoxide).")
target_group.add_argument("--device", default="LIFCL-40-9BG400C", help="FPGA device (LIFCL-40-9BG400C or LIFCL-40-8BG400CES).") target_group.add_argument("--device", default="LIFCL-40-9BG400C", help="FPGA device (LIFCL-40-9BG400C, LIFCL-40-8BG400CES, or LIFCL-40-8BG400CES2).")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.") target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
target_group.add_argument("--serial", default="serial", help="UART Pins (serial (requires R15 and R17 to be soldered) or serial_pmod[0-2]).") target_group.add_argument("--serial", default="serial", help="UART Pins (serial (requires R15 and R17 to be soldered) or serial_pmod[0-2]).")
target_group.add_argument("--programmer", default="radiant", help="Programmer (radiant or ecpprog).")
target_group.add_argument("--address", default=0x0, help="Flash address to program bitstream at.")
target_group.add_argument("--prog-target", default="direct", help="Programming Target (direct or flash).") target_group.add_argument("--prog-target", default="direct", help="Programming Target (direct or flash).")
builder_args(parser) builder_args(parser)
soc_core_args(parser) soc_core_args(parser)
@ -118,7 +120,10 @@ def main():
builder.build(**builder_kargs) builder.build(**builder_kargs)
if args.load: if args.load:
prog = soc.platform.create_programmer(args.prog_target) prog = soc.platform.create_programmer(args.prog_target, args.programmer)
if args.programmer == "ecpprog" and args.prog_target == "flash":
prog.flash(address=args.address, bitstream=builder.get_bitstream_filename(mode="sram"))
else:
prog.load_bitstream(builder.get_bitstream_filename(mode="sram")) prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if __name__ == "__main__": if __name__ == "__main__":