Hardware/litex-boards
1
0
Fork 0
mirror of https://github.com/litex-hub/litex-boards.git synced 2025-01-03 03:43:36 -05:00
Code Issues Projects Releases Packages Wiki Activity

targets/colorlight_5a_75b: switch to SoCCore, CPU and Etherbone working :)

Browse source 
Tested with:
./colorlight_5a_75b.py --cpu-type=picorv32 --uart-name=crossover --with-etherbone --csr-csv=csr.csv

Load with following script:
#!/usr/bin/env python3

# Load ---------------------------------------------------------------------------------------------

def load():
    import os
    f = open("openocd.cfg", "w")
    f.write(
"""
interface ftdi
ftdi_vid_pid 0x0403 0x6011
ftdi_channel 0
ftdi_layout_init 0x0098 0x008b
reset_config none
adapter_khz 25000
jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
""")
    f.close()
    os.system("openocd -f openocd.cfg -c \"transport select jtag; init; svf soc_etherbonesoc_colorlight_5a_75b/gateware/top.svf; exit\"")
    exit()

if __name__ == "__main__":
    load()


Then start lxserver:
lxserver --udp

And run following script:

#!/usr/bin/env python3

import sys

from litex import RemoteClient

wb = RemoteClient()
wb.open()

# # #

while True:
    if wb.regs.uart_xover_rxempty.read() == 0:
        print(chr(wb.regs.uart_xover_rxtx.read()), end="")
        sys.stdout.flush()

# # #

wb.close()
This commit is contained in:
Florent Kermarrec 2020-01-22 15:56:21 +01:00
parent c07e4a6b3a
commit dcc65b347d
1 changed files with 3 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
litex_boards/partner/targets/colorlight_5a_75b.py
View file

@ -41,13 +41,13 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCMini):
class BaseSoC(SoCCore):
def __init__(self, revision, **kwargs):
platform = colorlight_5a_75b.Platform(revision=revision)
sys_clk_freq = int(125e6)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)