mirror of
https://github.com/litex-hub/litex-boards.git
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platforms: Add LambdaConcept's PCIe Screamer/M2.
This commit is contained in:
Florent Kermarrec
parent
00ff61baa9
commit
dd27a3473b
2 changed files with 196 additions and 0 deletions
108
litex_boards/platforms/lambdaconcept_pcie_screamer.py
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108
litex_boards/platforms/lambdaconcept_pcie_screamer.py
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2016-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk.
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("clk100", 0, Pins("R4"), IOStandard("LVCMOS33")),
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# Leds.
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("user_led", 0, Pins("AB1"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("AB8"), IOStandard("LVCMOS33")),
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# Buttons.
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("user_btn", 0, Pins("AA1"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("AB6"), IOStandard("LVCMOS33")),
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# Serial.
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("serial", 0,
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Subsignal("tx", Pins("T1")),
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Subsignal("rx", Pins("U1")),
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IOStandard("LVCMOS33"),
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),
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# DDR3 SDRAM.
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("ddram", 0,
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Subsignal("a", Pins(
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"M2 M5 M3 M1 L6 P1 N3 N2",
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"M6 R1 L5 N5 N4 P2 P6"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("L3 K6 L4"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("J4"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("K3"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("L1"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("G3 F1"), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"G2 H4 H5 J1 K1 H3 H2 J5",
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"E3 B2 F3 D2 C2 A1 E2 B1"),
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IOStandard("SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_50")),
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Subsignal("dqs_p", Pins("K2 E1"), IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("J2 D1"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("P5"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("P4"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("J6"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("K4"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("G1"), IOStandard("SSTL15")),
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Misc("SLEW=FAST"),
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),
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# PCIe.
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("pcie_x1", 0,
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Subsignal("rst_n", Pins("AB7"), IOStandard("LVCMOS33")),
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Subsignal("clk_p", Pins("F6")),
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Subsignal("clk_n", Pins("E6")),
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Subsignal("rx_p", Pins("B10")),
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Subsignal("rx_n", Pins("A10")),
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Subsignal("tx_p", Pins("B6")),
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Subsignal("tx_n", Pins("A6"))
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),
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# USB-FIFO.
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("usb_fifo_clock", 0, Pins("D17"), IOStandard("LVCMOS33")),
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("usb_fifo", 0,
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Subsignal("rst", Pins("K22")),
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Subsignal("data", Pins(
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"A16 F14 A15 F13 A14 E14 A13 E13",
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"B13 C15 C13 C14 B16 E17 B15 F16",
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"A20 E18 B20 F18 D19 D21 E19 E21",
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"A21 B21 A19 A18 F20 F19 B18 B17")),
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Subsignal("be", Pins("K16 L16 G20 H20")),
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Subsignal("rxf_n", Pins("M13")),
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Subsignal("txe_n", Pins("L13")),
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Subsignal("rd_n", Pins("K19")),
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Subsignal("wr_n", Pins("M15")),
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Subsignal("oe_n", Pins("K18")),
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Subsignal("siwua", Pins("M16")),
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IOStandard("LVCMOS33"),
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Misc("SLEW=FAST")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7a35t-fgg484-2", _io, toolchain="vivado")
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGRATE 40 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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88
litex_boards/platforms/lambdaconcept_pcie_screamer_m2.py
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88
litex_boards/platforms/lambdaconcept_pcie_screamer_m2.py
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@ -0,0 +1,88 @@
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2016-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk.
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("clk100", 0, Pins("R2"), IOStandard("LVCMOS33")),
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# Leds.
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("user_led", 0, Pins("V17"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("U17"), IOStandard("LVCMOS33")),
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# Serial.
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("serial", 0,
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Subsignal("tx", Pins("U4")),
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Subsignal("rx", Pins("V4")),
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IOStandard("LVCMOS33"),
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),
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# PCIe.
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("pcie_x1", 0,
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Subsignal("rst_n", Pins("M1"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
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Subsignal("clk_p", Pins("D6")),
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Subsignal("clk_n", Pins("D5")),
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Subsignal("rx_p", Pins("E4")),
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Subsignal("rx_n", Pins("E3")),
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Subsignal("tx_p", Pins("H2")),
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Subsignal("tx_n", Pins("H1"))
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),
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("pcie_x4", 0,
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Subsignal("rst_n", Pins("M1"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
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Subsignal("clk_p", Pins("D6")),
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Subsignal("clk_n", Pins("D5")),
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Subsignal("rx_p", Pins("E4 A4 C4 G4")),
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Subsignal("rx_n", Pins("E3 A3 C3 G3")),
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Subsignal("tx_p", Pins("H2 F2 D2 B2")),
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Subsignal("tx_n", Pins("H1 F1 D1 B1"))
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),
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# USB-FIFO.
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("usb_fifo_clock", 0, Pins("E13"), IOStandard("LVCMOS33")),
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("usb_fifo", 0,
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Subsignal("rst", Pins("U15")),
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Subsignal("data", Pins(
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"B9 A9 C9 A10 B10 B11 A12 B12",
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"A13 A14 B14 A15 B15 B16 A17 B17",
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"C17 C18 D18 E17 E18 E16 F18 F17",
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"G17 H18 D13 C14 D14 D15 C16 D16")),
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Subsignal("be", Pins("L18 M17 N18 N17")),
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Subsignal("rxf_n", Pins("R18")),
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Subsignal("txe_n", Pins("P18")),
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Subsignal("rd_n", Pins("R16")),
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Subsignal("wr_n", Pins("T18")),
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Subsignal("oe_n", Pins("T15")),
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Subsignal("siwua", Pins("R17")),
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IOStandard("LVCMOS33"),
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Misc("SLEW=FAST")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7a35t-csg325-2", _io, toolchain="vivado")
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGRATE 40 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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