Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Olimex GateMate A1 EVB: new Board

This commit is contained in:
Gwenhael Goavec-Merou 2024-03-02 11:02:39 +01:00
parent 85971de42e
commit e1e989acac
3 changed files with 238 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
README.md
View File

@ -192,6 +192,7 @@ Some of the suported boards, see yours? Give LiteX-Boards a try!
├── numato_nereid
├── numato_tagus
├── ocp_tap_timecard
├── olimex_gatemate_a1_evb
├── opalkelly_xem8320
├── pano_logic_g2
├── qmtech_10cl006

125
litex_boards/platforms/olimex_gatemate_a1_evb.py Normal file
View File

@ -0,0 +1,125 @@
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2024 Gwenhael Goavec-merou<gwenhael.goavec-merou@trabucayre.com>
# SPDX-License-Identifier: BSD-2-Clause
# Board documentation/schematics:
# https://www.olimex.com/Products/FPGA/GateMate/GateMateA1-EVB/open-source-hardware
from litex.build.generic_platform import *
from litex.build.colognechip.platform import CologneChipPlatform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk0", 0, Pins("IO_SB_A8"), Misc("SCHMITT_TRIGGER=true")),
# Leds
("user_led_n", 0, Pins("IO_SB_B6")),
# Button
("user_btn_n", 0, Pins("IO_SB_B7")),
# Serial.
("serial", 0,
Subsignal("tx", Pins("IO_SA_B6")),
Subsignal("rx", Pins("IO_SA_A6"))
),
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("IO_WA_A8")),
Subsignal("clk", Pins("IO_WA_B8")),
Subsignal("miso", Pins("IO_WA_B7")),
Subsignal("mosi", Pins("IO_WA_A7")),
Subsignal("wp", Pins("IO_WA_B6")),
Subsignal("hold", Pins("IO_WA_B6")),
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("IO_WA_A8")),
Subsignal("clk", Pins("IO_WA_B8")),
Subsignal("dq", Pins("IO_WA_B7 IO_WA_A7 IO_WA_B6 IO_WA_B6")),
),
# QPSRAM
("qpsram", 0,
Subsignal("ck", Pins("IO_WC_B4")),
Subsignal("cs_n", Pins("IO_WC_A4")),
Subsignal("data", Pins("IO_WC_A5 IO_WC_B5 IO_WC_A6 IO_WC_B6 IO_WC_A7 IO_WC_B7 IO_WC_A8 IO_WC_B8")),
),
# VGA
("vga", 0,
Subsignal("hsync_n", Pins("IO_WB_A1")),
Subsignal("vsync_n", Pins("IO_WB_B1")),
Subsignal("r", Pins("IO_WB_B3 IO_WB_A3 IO_WB_B2 IO_WB_A2")),
Subsignal("g", Pins("IO_WB_B5 IO_WB_A5 IO_WB_B4 IO_WB_A4")),
Subsignal("b", Pins("IO_WB_B7 IO_WB_A7 IO_WB_B6 IO_WB_A6")),
),
# PS2 ports.
("ps2", 0,
Subsignal("clk", Pins("IO_WB_A0")),
Subsignal("data", Pins("iO_WB_B0")),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("PMOD", "IO_EA_A4 IO_EA_A5 IO_EA_A6 IO_EA_A7 IO_EA_B4 IO_EA_B5 IO_EA_B6 IO_EA_B7"),
# 3V3 GND
("UEXT", "-------- -------- IO_EA_A0 IO_EA_B0 IO_EA_A1 IO_EA_B1 IO_EA_A2 IO_EA_B2 IO_EA_A3 IO_EA_B3"),
["bank_na1",
"---", # 0
# VDD_NA GND ( 1-10)
" -------- -------- IO_NA_A0 IO_NA_B0 IO_NA_A1 IO_NA_B1 IO_NA_A2 IO_NA_B2 IO_NA_A3 IO_NA_B3",
# (11-20)
" IO_NA_A4 IO_NA_B4 IO_NA_A5 IO_NA_B5 IO_NA_A6 IO_NA_B6 IO_NA_A7 IO_NA_B7 IO_NA_A8 IO_NA_B8",
],
["bank_nb1",
"---", # 0
# VDD_NB GND ( 1-10)
" -------- -------- IO_NB_A0 IO_NB_B0 IO_NB_A1 IO_NB_B1 IO_NB_A2 IO_NB_B2 IO_NB_A3 IO_NB_B3",
# (11-20)
" IO_NB_A4 IO_NB_B4 IO_NB_A5 IO_NB_B5 IO_NB_A6 IO_NB_B6 IO_NB_A7 IO_NB_B7 IO_NB_A8 IO_NB_B8",
],
["bank_eb1",
"---", # 0
# VDD_EB GND ( 1-10)
" -------- -------- IO_EB_A8 IO_EB_B8 IO_EB_A7 IO_EB_B7 IO_EB_A6 IO_EB_B6 IO_EB_A5 IO_EB_B5",
# (11-20)
" IO_EB_A4 IO_EB_B4 IO_EB_A3 IO_EB_B3 IO_EB_A2 IO_EB_B2 IO_EB_A1 IO_EB_B1 IO_EB_A0 IO_EB_B0",
],
["bank_misc1",
"---", # 0
# 2V5 1V8 ( 1-10)
" -------- --------- IO_WA_B5 IO_WC_B3 IO_EA_A8 IO_WC_A3 IO_EA_B8 IO_WC_B2 IO_WB_A8 IO_WC_A2",
# SER_CLK_N (11-20)
" IO_WB_B8 IO_WC_B1 IO_SB_B3 IO_WC_A1 IO_SB_A3 IO_WC_B0 IO_SB_A2 IO_WC_A0 IO_SB_A2 ---------",
# SER_CLK_P SER_TX_P SER_TX_N SER_RX_N SER_RX_P (21-30)
" IO_SB_B1 --------- IO_SB_A1 -------- IO_SB_B0 -------- IO_SB_A0 -------- IO_SB_A2 ---------",
# GND GND (31-34)
" IO_SB_A8 IO_SB_A5 -------- --------",
],
]
# Platform -----------------------------------------------------------------------------------------
class Platform(CologneChipPlatform):
default_clk_name = "clk0"
default_clk_period = 1e9/10e6
def __init__(self, toolchain="colognechip"):
CologneChipPlatform.__init__(self, "CCGM1A1", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return OpenFPGALoader(cable="dirtyJtag")
def do_finalize(self, fragment):
CologneChipPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk0", loose=True), 1e9/10e6)

112
litex_boards/targets/olimex_gatemate_a1_evb.py Executable file
View File

@ -0,0 +1,112 @@
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2024 Gwenhael Goavec-merou<gwenhael.goavec-merou@trabucayre.com>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.gen import *
from litex_boards.platforms import olimex_gatemate_a1_evb
from litex.build.io import CRG
from litex.soc.cores.clock.colognechip import GateMatePLL
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.build.generic_platform import Pins
from litex.soc.cores.led import LedChaser
from litex.soc.cores.video import VideoVGAPHY
# CRG ----------------------------------------------------------------------------------------------
class _CRG(LiteXModule):
def __init__(self, platform, sys_clk_freq, with_video_terminal):
self.rst = Signal()
rst_n = Signal()
self.cd_sys = ClockDomain()
if with_video_terminal:
self.cd_vga = ClockDomain()
# # #
# Clk / Rst
clk0 = platform.request("clk0")
self.rst = ~platform.request("user_btn_n", 0)
self.specials += Instance("CC_USR_RSTN", o_USR_RSTN = rst_n)
# PLL
self.pll = pll = GateMatePLL(perf_mode="economy")
self.comb += pll.reset.eq(~rst_n | self.rst)
pll.register_clkin(clk0, 10e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
if with_video_terminal:
self.pll_video = pll_video = GateMatePLL(perf_mode="economy")
self.comb += pll_video.reset.eq(~rst_n | self.rst)
pll_video.register_clkin(clk0, 10e6)
pll_video.create_clkout(self.cd_vga, 65e6)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=24e6,
with_video_terminal = False,
with_led_chaser = True,
**kwargs):
platform = olimex_gatemate_a1_evb.Platform()
# CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq, with_video_terminal)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on GateMate EVB", **kwargs)
# Video Terminal ---------------------------------------------------------------------------
if with_video_terminal:
vga_pads = platform.request("vga")
self.videophy = VideoVGAPHY(vga_pads, clock_domain="vga")
self.add_video_terminal(phy=self.videophy, timings="1024x768@60Hz", clock_domain="vga")
#self.add_video_colorbars(phy=self.videophy, timings="1024x768@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.leds = LedChaser(
pads = platform.request_all("user_led_n"),
sys_clk_freq = sys_clk_freq)
# Build --------------------------------------------------------------------------------------------
def main():
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=olimex_gatemate_a1_evb.Platform, description="LiteX SoC on Olimex Gatemate A1 EVB")
parser.add_target_argument("--sys-clk-freq", default=24e6, type=float, help="System clock frequency.")
parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = args.sys_clk_freq,
with_video_terminal = args.with_video_terminal,
**parser.soc_argdict)
builder = Builder(soc, **parser.builder_argdict)
if args.build:
builder.build(**parser.toolchain_argdict)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer()
prog.flash(0, builder.get_bitstream_filename(mode="flash"))
if __name__ == "__main__":
main()