Basic SoC for Opal Kelly XEM8320
This commit is contained in:
AEW2015
parent
f400179b5b
commit
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Andrew Elbert Wilson <Andrew.E.Wilson@ieee.org>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("sys_clk100", 0,
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Subsignal("p", Pins("T24"), IOStandard("LVDS")),
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Subsignal("n", Pins("U24"), IOStandard("LVDS"))
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),
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("ddr_clk100", 0,
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Subsignal("p", Pins("AD20"), IOStandard("LVDS")),
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Subsignal("n", Pins("AE20"), IOStandard("LVDS"))
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),
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#NO RESET, maybe use okHOST USB later
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#("cpu_reset", 0, Pins("AN8"), IOStandard("LVCMOS18")),
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# Leds
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("user_led", 0, Pins("G19"), IOStandard("LVCMOS18")),
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("user_led", 1, Pins("B16"), IOStandard("LVCMOS18")),
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("user_led", 2, Pins("F22"), IOStandard("LVCMOS18")),
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("user_led", 3, Pins("E22"), IOStandard("LVCMOS18")),
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("user_led", 4, Pins("M24"), IOStandard("LVCMOS18")),
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("user_led", 5, Pins("G22"), IOStandard("LVCMOS18")),
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# Opal Kelly Host USBC interface
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("okHost", 0, # Uses the FrontPanel API
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Subsignal("okAA", Pins("T19")),
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Subsignal("okHU", Pins("U20 U26 T22")),
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Subsignal("okUH", Pins("V23 T23 U22 U25 U21")),
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Subsignal("okUHU", Pins("P26 P25 R26 R25 R23 R22 P21 P20",
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"R21 R20 P23 N23 T25 N24 N22 V26",
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"N19 V21 N21 W20 W26 W19 Y25 Y26",
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"Y22 V22 W21 AA23 Y23 AA24 W25 AA25")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS18"),
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),
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# TODO: Add SMA & SFP+
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# DDR4 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"AD18 AE17 AB17 AE18 AD19 AF17 Y17 AE16",
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"AA17 AC17 AC19 AC16 AF20 AD16"),
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IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("AC18 AF18"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("AB19"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("AA18"), IOStandard("SSTL12_DCI")),
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Subsignal("cas_n", Pins("AF19"), IOStandard("SSTL12_DCI")),
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Subsignal("we_n", Pins("AA19"), IOStandard("SSTL12_DCI")),
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Subsignal("cs_n", Pins("AF22"), IOStandard("SSTL12_DCI")),
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Subsignal("act_n", Pins("Y18"), IOStandard("SSTL12_DCI")),
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Subsignal("dm", Pins("AE25 AE22"),
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IOStandard("POD12_DCI")),
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Subsignal("dq", Pins(
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"AF24 AB25 AB26 AC24 AF25 AB24 AD24 AD25",
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"AB21 AE21 AE23 AD23 AC23 AD21 AC22 AC21"),
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IOStandard("POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_p", Pins("AC26 AA22"),
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IOStandard("DIFF_POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_n", Pins("AD26 AB22"),
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IOStandard("DIFF_POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("clk_p", Pins("Y20"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("clk_n", Pins("Y21"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("cke", Pins("AA20"), IOStandard("SSTL12_DCI")),
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Subsignal("odt", Pins("AB20"), IOStandard("SSTL12_DCI")),
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Subsignal("reset_n", Pins("AE26"), IOStandard("LVCMOS12")),
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Misc("SLEW=FAST"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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# TODO: SYZYGY Connectors & SYZYGY to PMODS!
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_connectors = [
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("pmod1", "AC14 AC13 AF15 AF14 AF13 AE13 H13 J13"),
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("pmod2", "AB15 AB16 W14 J14 AE15 W15 Y15 J15"),
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("pmod3", "G14 H14 W13 W12 AA13 Y13 H12 J12"),
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("pmod4", "AD14 AD13 W16 AD15 AB14 AA14 Y16 AA15"),
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]
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def dvi_pmod_io(pmoda,pmodb):
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return [
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("dvi", 0,
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Subsignal("clk", Pins(f"{pmodb}:1")),
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Subsignal("de", Pins(f"{pmodb}:6")),
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Subsignal("hsync", Pins(f"{pmodb}:3")),
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Subsignal("vsync", Pins(f"{pmodb}:7")),
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Subsignal("b", Pins(f"{pmoda}:5 {pmoda}:1 {pmoda}:4 {pmoda}:0")),
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Subsignal("g", Pins(f"{pmoda}:7 {pmoda}:3 {pmoda}:6 {pmoda}:2")),
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Subsignal("r", Pins(f"{pmodb}:2 {pmodb}:5 {pmodb}:4 {pmodb}:0")),
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IOStandard("LVCMOS33"),
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)
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]
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_dvi_pmod_io = dvi_pmod_io("pmod2","pmod1") # SDCARD PMOD on JD.
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def sdcard_pmod_io(pmod):
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return [
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# SDCard PMOD:
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# - https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
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# - https://github.com/antmicro/arty-expansion-board
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("spisdcard", 0,
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Subsignal("clk", Pins(f"{pmod}:3")),
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Subsignal("mosi", Pins(f"{pmod}:1"), Misc("PULLUP True")),
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Subsignal("cs_n", Pins(f"{pmod}:0"), Misc("PULLUP True")),
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Subsignal("miso", Pins(f"{pmod}:2"), Misc("PULLUP True")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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("sdcard", 0,
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Subsignal("data", Pins(f"{pmod}:2 {pmod}:4 {pmod}:5 {pmod}:0"), Misc("PULLUP True")),
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Subsignal("cmd", Pins(f"{pmod}:1"), Misc("PULLUP True")),
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Subsignal("clk", Pins(f"{pmod}:3")),
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Subsignal("cd", Pins(f"{pmod}:6")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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_sdcard_pmod_io = sdcard_pmod_io("pmod3") # SDCARD PMOD on JD.
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "sys_clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, toolchain="vivado"):
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XilinxPlatform.__init__(self, "xcau25p-ffvb676-2-e", _io, _connectors, toolchain=toolchain)
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("sys_clk100", loose=True), 1e9/100e6)
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self.add_period_constraint(self.lookup_request("ddr_clk100", loose=True), 1e9/100e6)
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 64]")
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@ -0,0 +1,64 @@
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interface ftdi
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ftdi_vid_pid 0x0403 0x6014
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ftdi_channel 0
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ftdi_layout_init 0x00e8 0x60eb
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reset_config none
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#openocd missing support, added to local cfg file
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set CHIP XCAU25P
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME xcu
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}
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# The cvarious chips in the Ultrascale family have different IR length.
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# Set $CHIP before including this file to determine the device.
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array set _XCU_DATA {
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XCAU25P {0x04A64093 6}
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}
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if { ![info exists CHIP] } {
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error "set CHIP to one of "[concat [array names _XCU_DATA]]
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}
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if { ![llength [array names _XCU_DATA $CHIP]] } {
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error "unknown CHIP: "$CHIP
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}
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set _EXPID [lindex $_XCU_DATA($CHIP) 0]
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set _IRLEN [lindex $_XCU_DATA($CHIP) 1]
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# the 4 top bits (28:31) are the die stepping/revisions. ignore it.
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jtag newtap $_CHIPNAME tap -irlen $_IRLEN -ignore-version -expected-id $_EXPID
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pld device virtex2 $_CHIPNAME.tap 1
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set XCU_JSHUTDOWN 0x0d
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set XCU_JPROGRAM 0x0b
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set XCU_JSTART 0x0c
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set XCU_BYPASS 0x3f
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proc xcu_program {tap} {
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global XCU_JSHUTDOWN XCU_JPROGRAM XCU_JSTART XCU_BYPASS
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irscan $tap $XCU_JSHUTDOWN
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irscan $tap $XCU_JPROGRAM
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runtest 60000
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#JSTART prevents this from working...
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#irscan $tap $XCU_JSTART
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runtest 2000
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irscan $tap $XCU_BYPASS
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runtest 2000
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}
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source [find cpld/jtagspi.cfg]
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adapter_khz 25000
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proc fpga_program {} {
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global _CHIPNAME
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xc7_program $_CHIPNAME.tap
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}
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@ -0,0 +1,152 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Andrew Elbert Wilson <Andrew.E.Wilson@ieee.org>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import opalkelly_xem8320
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.video import VideoDVIPHY
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from litedram.modules import MT40A512M16
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from litedram.phy import usddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain()
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self.clock_domains.cd_idelay = ClockDomain()
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self.clock_domains.cd_hdmi = ClockDomain()
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self.clock_domains.cd_hdmi5x = ClockDomain()
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# # #
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clk100 = platform.request("ddr_clk100")
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self.submodules.pll = pll = USMMCM(speedgrade=-2)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=False)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) #500
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pll.create_clkout(self.cd_hdmi, 25e6)
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pll.create_clkout(self.cd_hdmi5x, 5*25e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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# #option for second MMCM for video clocks
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# self.submodules.video_pll = video_pll = USMMCM(speedgrade=-2)
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# video_pll.reset.eq(self.rst)
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# video_pll.register_clkin(self.cd_sys.clk, sys_clk_freq)
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# video_pll.create_clkout(self.cd_hdmi, 25e6)
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# video_pll.create_clkout(self.cd_hdmi5x, 5*25e6)
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self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_sys4x, cd_sys=self.cd_sys)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False,
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eth_ip="192.168.1.50", with_led_chaser=True,
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**kwargs):
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platform = opalkelly_xem8320.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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kwargs["uart_name"] = "jtag_uart"
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# TODO: add okHost FrontPanel API for UART, Data streaing, and Debug
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on xem8320", **kwargs)
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# DDR4 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
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memtype = "DDR4",
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 500e6)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT40A512M16(sys_clk_freq, "1:4"),
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size = 0x40000000,
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# TODO: add SFP+ cages for ethernet
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# Ethernet / Etherbone ---------------------------------------------------------------------
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# if with_ethernet or with_etherbone:
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# self.submodules.ethphy = KU_1000BASEX(self.crg.cd_eth.clk,
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# data_pads = self.platform.request("sfp", 0),
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# sys_clk_freq = self.clk_freq)
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# self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
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# self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
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# if with_ethernet:
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# self.add_ethernet(phy=self.ethphy)
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# if with_etherbone:
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# self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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platform.add_extension(opalkelly_xem8320._dvi_pmod_io)
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self.submodules.videophy = VideoDVIPHY(platform.request("dvi"), clock_domain="hdmi")
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self.add_video_framebuffer(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on XEM8320")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
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#ethopts = target_group.add_mutually_exclusive_group()
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#ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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#with_ethernet = args.with_ethernet,
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#with_etherbone = args.with_etherbone,
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#eth_ip = args.eth_ip,
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#with_pcie = args.with_pcie,
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#with_sata = args.with_sata,
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**soc_core_argdict(args)
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)
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soc.platform.add_extension(opalkelly_xem8320._sdcard_pmod_io)
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soc.add_spi_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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if args.build:
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builder.build()
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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# TODO: add option for FrontPanel Programming
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if __name__ == "__main__":
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main()
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