litex_acorn_baseboard: Add some M2 signals and set devslp to 0.
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@ -71,6 +71,12 @@ _io = [
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IOStandard("LVCMOS33"),
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IOStandard("LVCMOS33"),
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),
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),
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# M2
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("m2_devslp", 0, Pins("U18"), IOStandard("LVCMOS33")),
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("m2_perst", 0, Pins("U17"), IOStandard("LVCMOS33")),
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("m2_pewake", 0, Pins("R16"), IOStandard("LVCMOS33")),
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("m2_pedet", 0, Pins("T17"), IOStandard("LVCMOS33")),
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# HDMI
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# HDMI
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("hdmi_i2c", 0,
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("hdmi_i2c", 0,
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Subsignal("scl", Pins("C9")),
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Subsignal("scl", Pins("C9")),
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@ -100,6 +100,9 @@ class BaseSoC(SoCCore):
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if with_lcd:
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if with_lcd:
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self.submodules.i2c = I2CMaster(platform.request("lcd"))
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self.submodules.i2c = I2CMaster(platform.request("lcd"))
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# M2 --------------------------------------------------------------------------------------
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self.comb += platform.request("m2_devslp").eq(0) # Enable SATA M2.
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# Build --------------------------------------------------------------------------------------------
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# Build --------------------------------------------------------------------------------------------
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def main():
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def main():
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