litex_acorn_baseboard: Add some M2 signals and set devslp to 0.

litex_boards/platforms/litex_acorn_baseboard.py

@@ -71,6 +71,12 @@ _io = [
         IOStandard("LVCMOS33"),
     ),
 
+    # M2
+    ("m2_devslp", 0, Pins("U18"), IOStandard("LVCMOS33")),
+    ("m2_perst",  0, Pins("U17"), IOStandard("LVCMOS33")),
+    ("m2_pewake", 0, Pins("R16"), IOStandard("LVCMOS33")),
+    ("m2_pedet",  0, Pins("T17"), IOStandard("LVCMOS33")),
+
     # HDMI
     ("hdmi_i2c", 0,
         Subsignal("scl", Pins("C9")),

litex_boards/targets/litex_acorn_baseboard.py

@@ -100,6 +100,9 @@ class BaseSoC(SoCCore):
         if with_lcd:
             self.submodules.i2c = I2CMaster(platform.request("lcd"))
 
+        # M2 --------------------------------------------------------------------------------------
+        self.comb += platform.request("m2_devslp").eq(0) # Enable SATA M2.
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():