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targets/ac701: reduce ddram pads to the first 4 modules.

This commit is contained in:
Florent Kermarrec 2020-09-05 11:46:01 +02:00
parent 76ac4a69a8
commit e4cdbe0f7a
1 changed files with 3 additions and 1 deletions
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4
litex_boards/targets/ac701.py
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@ -20,6 +20,7 @@ from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litedram.common import PHYPadsReducer
from litedram.modules import MT8JTF12864
from litedram.phy import s7ddrphy
@ -65,7 +66,8 @@ class BaseSoC(SoCCore):
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
pads = PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3]),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)