sipeed_tang_mega_138k_pro: Fix previous commit.
This commit is contained in:
Florent Kermarrec
parent
40c7a63e53
commit
e51b9eb392
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022-2023 Icenowy Zheng <uwu@icenowy.me>
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2023 Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.gowin.platform import GowinPlatform
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from litex.build.gowin.programmer import GowinProgrammer
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst.
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("clk50", 0, Pins("P16"), IOStandard("LVCMOS33")),
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("rst", 0, Pins("U4"), IOStandard("LVCMOS15")),
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# Serial.
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("serial", 0,
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Subsignal("rx", Pins("N16")),
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Subsignal("tx", Pins("P15")),
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IOStandard("LVCMOS33")
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),
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# SPIFlash.
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("spiflash", 0,
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Subsignal("cs_n", Pins("P18"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("H13"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("R15"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("R14"), IOStandard("LVCMOS33")),
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Subsignal("wp_n", Pins("P14"), IOStandard("LVCMOS33")),
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Subsignal("hold_n", Pins("N14"), IOStandard("LVCMOS33")),
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),
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# PCI Express
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("pcie", 0,
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Subsignal("rst_n", Pins("L23")),
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),
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# Leds
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("led_n", 0, Pins("J14"), IOStandard("LVCMOS33")),
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("led_n", 1, Pins("R26"), IOStandard("LVCMOS33")),
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("led_n", 2, Pins("L20"), IOStandard("LVCMOS33")),
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("led_n", 3, Pins("M25"), IOStandard("LVCMOS33")),
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("led_n", 4, Pins("N21"), IOStandard("LVCMOS33")),
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("led_n", 5, Pins("N23"), IOStandard("LVCMOS33")),
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("led_done", 0, Pins("W10"), IOStandard("LVCMOS33")),
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("led_ready", 0, Pins("V11"), IOStandard("LVCMOS33")),
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# DDR3 SDRAM H5TQ4G63EFR-RDC
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("ddram", 0,
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Subsignal("a", Pins(
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"N1 R1 R2 N2 P1 T2 N4 U1",
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"T4 T3 M1 P4 N3 U2 U5 "), # (M6 unused in 256x16)
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IOStandard("SSTL15"),
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Misc("DRIVE=12"),
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),
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Subsignal("ba", Pins("M4 L5 K3"), IOStandard("SSTL15"), Misc("DRIVE=12")),
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Subsignal("ras_n", Pins("H2"), IOStandard("SSTL15"), Misc("DRIVE=12")),
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Subsignal("cas_n", Pins("H1"), IOStandard("SSTL15"), Misc("DRIVE=12")),
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Subsignal("we_n", Pins("J3"), IOStandard("SSTL15"), Misc("DRIVE=12")),
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Subsignal("cs_n", Pins("L4"), IOStandard("SSTL15"), Misc("DRIVE=12")),
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Subsignal("dm", Pins("F4 H9 E3 A3"), IOStandard("SSTL15"), Misc("DRIVE=12")),
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Subsignal("dq", Pins(
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"G4 J6 L8 G5 K7 J5 K8 K6",
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"E6 H8 H6 G8 D6 F8 G6 F7",
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"C4 F3 B4 E5 D3 D5 A4 D4",
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"E1 A2 G2 C2 F2 E2 G1 D1"),
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IOStandard("SSTL15"),
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Misc("DRIVE=12"),
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),
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Subsignal("dqs_p", Pins("J4 H7 B5 C1"), IOStandard("SSTL15D"), Misc("DRIVE=8")),
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Subsignal("dqs_n", Pins("H4 G7 A5 B1"), IOStandard("SSTL15D"), Misc("DRIVE=8")),
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Subsignal("clk_p", Pins("M2"), IOStandard("SSTL15D"), Misc("DRIVE=8")),
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Subsignal("clk_n", Pins("L2"), IOStandard("SSTL15D"), Misc("DRIVE=8")),
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Subsignal("cke", Pins("L3"), IOStandard("SSTL15"), Misc("DRIVE=4")),
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Subsignal("odt", Pins("J1"), IOStandard("SSTL15"), Misc("DRIVE=12")),
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Subsignal("reset_n", Pins("N8"), IOStandard("SSTL15"), Misc("DRIVE=12")),
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Misc("PULL_MODE=NONE BANK_VCCIO=1.5"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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["J1",
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# -------------------------------------------------------------
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"---", # 0
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# GND GND ( 1-10).
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" ---- ---- AC26 AC24 AB26 AB24 AB25 AA23 AA24 AA22",
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# GND GND ( 11-20).
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" AA25 Y23 Y25 Y22 Y26 W24 W25 V24 ---- ----",
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# ( 21-30).
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" W26 W23 V26 V23 U26 U24 U25 L24 R26 Y20",
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# ( 31-40).
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" P26 W20 P19 W19 N19 V19 M20 V22 L20 U22",
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# 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V ( 41-50).
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" ---- ---- ---- ---- ---- ---- ---- ---- ---- ----",
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# 5V 5V 5V 5V 5V 5V 3V3 5V 3V3 5V ( 51-60).
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" ---- ---- ---- ---- ---- ---- ---- ---- ---- ----",
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# GND GND GND ( 61-70).
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" ---- ---- R15 N16 L20 E17 ---- E18 M21 N17",
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# GND GND GND ( 71-80).
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" M22 M24 ---- M25 N23 N22 N24 N21 ---- ----",
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# ( 81-90).
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" N26 L22 M26 L23 C19 K22 D19 K23 K25 K21",
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# ( 91-100).
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" K26 J21 J25 N18 J26 M19 H26 L19 G26 K18",
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# GND GND (101-110).
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" ---- ---- M15 J24 L15 H24 K20 J23 J20 H23",
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# GND GND (111-120).
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" E26 D23 D26 D24 C26 C22 B26 C23 ---- ----",
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],
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["J2",
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# -------------------------------------------------------------
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"---", # 0
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# GND GND VCCO VCCO VCCO VCCO GND GND ( 1-10).
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" ---- ---- ---- ---- ---- ---- ---- ---- V21 P25",
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# GND ( 11-20).
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" U21 R25 ---- T25 U20 T24 T20 T23 U19 R23",
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# GND ( 21-30).
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" T19 P24 W18 P23 V18 P21 R18 ---- T18 Y21",
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# GND ( 31-40).
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" T17 W21 U17 ---- U14 V17 V14 V16 T15 U16",
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# GND GND ( 41-50).
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" T14 U15 Y9 AB15 AB7 W9 ---- ---- R17 J15",
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# GND GND GND GND ( 51-60).
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" R16 J14 ---- ---- R11 AE16 R12 U4 ---- ----",
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# GND GND ( 61-70).
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" AD14 AA11 AC14 AB11 ---- ---- AB13 AC10 AA13 AD10",
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# GND GND GND GND ( 71-80).
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" ---- ---- AF13 Ac8 AE13 AD8 ---- ---- AF11 AE9",
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# GND GND GND GND ( 81-90).
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" AE11 AF9 ---- ---- AD12 AE7 AC12 AF7 ---- ----",
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# GND GND ( 91-100).
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" W4 AB1 V4 AC1 ---- ---- AA3 AE5 Y3 AF5",
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# GND GND GND GND (101-110).
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" ---- ---- W3 AE3 V3 AF3 ---- ---- AA2 AE2",
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# GND GND GND GND (111-120).
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" Y2 AF2 ---- ---- W1 AD1 V1 AE1 ---- ----",
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],
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["J3",
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# -------------------------------------------------------------
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"---", # 0
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# GND GND GND ( 1-10).
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" ---- ---- B25 A24 A25 A23 C24 ---- B24 H22",
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# GND GND ( 11-20).
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" E25 H21 D25 F20 G24 G19 F24 ---- ---- F19",
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# ( 21-30).
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" E22 F18 H17 M17 F23 M16 E23 J16 B22 K15",
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# GND ( 31-40).
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" A22 ---- E21 F22 D21 G22 E20 G21 D20 G20",
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# GND GND ( 41-50).
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" ---- ---- D18 H19 C18 J19 C17 F25 B17 G25",
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# GND ( 51-60).
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" E16 ---- D16 H18 G17 J18 F17 K17 L17 K16",
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# GND ( 61-70).
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" L18 F15 ---- G15 H14 G16 H15 H16 C21 L14",
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# GND GND GND ( 71-80).
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" B21 M14 B20 ---- A20 P11 ---- N12 B19 ----",
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# TCK GND TDI TDO TMS GND GND ( 81-90).
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" A19 H12 ---- H10 A17 J10 A18 H11 ---- ----",
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# GND GND ( 91-100).
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" F11 F13 E11 E13 ---- ---- D10 C12 C10 D12",
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# GND GND GND GND (101-110).
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" ---- ---- D8 C14 C8 D14 ---- ---- B9 A13",
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# GND GND GND GND (111-120).
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" A9 B13 ---- ---- B7 P11 A7 N12 ---- ----",
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],
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]
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# Dock IOs -----------------------------------------------------------------------------------------
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# Note: SOM.J1 -> dock.J6 odd/even revert
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# SOM.J2 -> dock.J7 odd/even revert
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# SOM.J3 -> dock.J8 odd/even revert
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_dock_io = [
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("btn_n", 0, Pins( "J3:60"), IOStandard("LVCMOS33")),
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("btn_n", 1, Pins( "J3:62"), IOStandard("LVCMOS33")),
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("btn_n", 2, Pins( "J3:64"), IOStandard("LVCMOS33")),
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("btn_n", 3, Pins( "J3:66"), IOStandard("LVCMOS33")),
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# FAN
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("fan", 0,
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Subsignal("pwm", Pins("T18")),
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Subsignal("tac", Pins("T17")),
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IOStandard("LVCMOS33")
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),
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("led_ws2812", 0, Pins("H16"), IOStandard("LVCMOS33")),
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# LCD
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("lcd", 0,
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Subsignal("r", Pins("H19 J19 G25 H18 J18 K17")),
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Subsignal("g", Pins("J16 K15 F22 G22 G21 G20")),
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Subsignal("b", Pins("F20 G19 F19 F18 M17 M16")),
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Subsignal("en", Pins("A24")),
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Subsignal("clk", Pins("H21")),
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IOStandard("LVCMOS33"),
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Misc("PULL_MODE=NONE DRIVE=24 BANK_VCCIO=3.3")
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),
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# HDMI In
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("hdmi_in", 0,
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Subsignal("clk_p", Pins("J1:107")),
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Subsignal("clk_n", Pins("J1:109")),
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Subsignal("data0_p", Pins("J1:87")),
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Subsignal("data0_n", Pins("J1:85")),
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Subsignal("data1_p", Pins("J1:103")),
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Subsignal("data1_n", Pins("J1:105")),
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Subsignal("data2_p", Pins("J1:93")),
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Subsignal("data2_n", Pins("J1:95")),
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Subsignal("hdp", Pins("J1:99")),
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#Subsignal("scl", Pins("J1:89")),
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#Subsignal("sda", Pins("J1:91")),
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#Subsignal("cec", Pins("J1:97")),
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IOStandard("LVCMOS33D"),
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Misc("PULL_MODE=NONE DRIVE=8")
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),
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# HDMI Out
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("hdmi_out", 0,
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Subsignal("clk_p", Pins("J1:14")),
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Subsignal("clk_n", Pins("J1:12")),
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Subsignal("data0_p", Pins("J1:6")),
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Subsignal("data0_n", Pins("J1:4")),
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Subsignal("data1_p", Pins("J1:18")),
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Subsignal("data1_n", Pins("J1:16")),
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Subsignal("data2_p", Pins("J1:10")),
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Subsignal("data2_n", Pins("J1:8")),
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Subsignal("hdp", Pins("J2:39")),
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#Subsignal("scl", Pins("J1:89")),
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#Subsignal("sda", Pins("J1:91")),
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#Subsignal("cec", Pins("J2:41")),
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IOStandard("LVCMOS33D"),
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Misc("PULL_MODE=NONE DRIVE=8")
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),
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("sdram_clock", 0, Pins("V23"), IOStandard("LVCMOS33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"V19 W19 U22 V22 Y25 AA25 AA24 AB25",
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"AB26 AC26 Y20 U25 U24")),
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Subsignal("dq", Pins(
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"U16 V16 U15 V17 W21 Y21 P21 U17",
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"P25 W23 T25 R25 R23 T23 P24 P23")),
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Subsignal("ba", Pins("V26 W20")),
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Subsignal("cas_n", Pins("W26")),
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Subsignal("cs_n", Pins("U26")),
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Subsignal("ras_n", Pins("W25")),
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Subsignal("we_n", Pins("Y26")),
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IOStandard("LVCMOS33"),
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Misc("PULL_MODE=UP")
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),
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# RGMII Ethernet
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("eth_clocks", 0,
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Subsignal("tx", Pins("H24")),
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Subsignal("rx", Pins("C23")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("E17")),
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Subsignal("mdio", Pins("K22")),
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Subsignal("mdc", Pins("K23")),
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Subsignal("rx_ctl", Pins("C22")),
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Subsignal("rx_data", Pins("B26 C26 D26 E26")),
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Subsignal("tx_ctl", Pins("J24")),
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Subsignal("tx_data", Pins("K21 J21 L19 K18")),
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IOStandard("LVCMOS33"),
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),
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("ephy_clk", 0, Pins("E18"), IOStandard("LVCMOS33")),
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]
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_dock_connectors = [
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["sdram_connector",
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# -------------------------------------------------------------
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"---", # 0
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# ( 1-10).
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" U16 V16 U15 V17 W21 Y21 P21 U17 P23 P24",
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# 5V GND (11-20).
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" --- --- T23 R23 R25 T25 W23 P25 U24 V23",
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# (21-30).
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" AC26 U25 AB25 AB26 AA25 AA24 Y26 Y25 L22 M24",
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# (31-40).
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" W26 W25 U26 V26 W20 Y20 V19 W19 U22 V22",
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],
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(GowinPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self, dock="standard", toolchain="gowin"):
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GowinPlatform.__init__(self, "GW5AST-LV138FPG676AES", _io, _connectors, toolchain=toolchain, devicename="GW5AST-138B")
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self.add_extension(_dock_io)
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self.add_connector(_dock_connectors)
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self.toolchain.options["use_ready_as_gpio"] = 1
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self.toolchain.options["use_done_as_gpio"] = 1
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self.toolchain.options["use_mspi_as_gpio"] = 1
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self.toolchain.options["use_sspi_as_gpio"] = 1
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self.toolchain.options["use_cpu_as_gpio"] = 1
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self.toolchain.options["rw_check_on_ram"] = 1
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self.toolchain.options["bit_security"] = 0
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self.toolchain.options["bit_encrypt"] = 0
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self.toolchain.options["bit_compress"] = 0
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def create_programmer(self, kit="openfpgaloader"):
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return OpenFPGALoader(cable="ft2232")
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def do_finalize(self, fragment):
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GowinPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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