mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
targets/pcie: remove soft reset.
This commit is contained in:
Florent Kermarrec
parent
1356ebb416
commit
e91a5d6b82
4 changed files with 4 additions and 40 deletions
litex_boards/targets
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@ -26,7 +26,6 @@ import argparse
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import sys
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from migen import *
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from migen.genlib.misc import WaitTimer
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from litex_boards.platforms import acorn_cle_215
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@ -52,10 +51,8 @@ from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class CRG(Module, AutoCSR):
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class CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = CSR()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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@ -64,14 +61,8 @@ class CRG(Module, AutoCSR):
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# Clk/Rst
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clk200 = platform.request("clk200")
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# Delay software reset by 10us to ensure write has been acked on PCIe.
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rst_delay = WaitTimer(int(10e-6*sys_clk_freq))
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self.submodules += rst_delay
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self.sync += If(self.rst.re, rst_delay.wait.eq(1))
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# PLL
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self.submodules.pll = pll = S7PLL()
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self.comb += pll.reset.eq(rst_delay.done)
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pll.register_clkin(clk200, 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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@ -9,7 +9,6 @@ import argparse
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import sys
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from migen import *
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from migen.genlib.misc import WaitTimer
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from litex_boards.platforms import aller
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@ -35,10 +34,8 @@ from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class CRG(Module, AutoCSR):
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class CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = CSR()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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@ -47,14 +44,8 @@ class CRG(Module, AutoCSR):
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# Clk/Rst
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clk100 = platform.request("clk100")
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# Delay software reset by 10us to ensure write has been acked on PCIe.
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rst_delay = WaitTimer(int(10e-6*sys_clk_freq))
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self.submodules += rst_delay
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self.sync += If(self.rst.re, rst_delay.wait.eq(1))
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# PLL
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self.submodules.pll = pll = S7PLL()
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self.comb += pll.reset.eq(rst_delay.done)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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@ -9,7 +9,6 @@ import argparse
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import sys
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from migen import *
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from migen.genlib.misc import WaitTimer
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from litex_boards.platforms import nereid
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@ -34,10 +33,8 @@ from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class CRG(Module, AutoCSR):
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class CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = CSR()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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@ -45,14 +42,8 @@ class CRG(Module, AutoCSR):
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# Clk/Rst
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clk100 = platform.request("clk100")
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# Delay software reset by 10us to ensure write has been acked on PCIe.
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rst_delay = WaitTimer(int(10e-6*sys_clk_freq))
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self.submodules += rst_delay
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self.sync += If(self.rst.re, rst_delay.wait.eq(1))
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# PLL
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self.submodules.pll = pll = S7PLL()
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self.comb += pll.reset.eq(rst_delay.done)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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@ -9,7 +9,6 @@ import argparse
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import sys
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from migen import *
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from migen.genlib.misc import WaitTimer
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from litex_boards.platforms import tagus
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@ -35,10 +34,8 @@ from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class CRG(Module, AutoCSR):
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class CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = CSR()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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@ -47,14 +44,8 @@ class CRG(Module, AutoCSR):
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# Clk/Rst
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clk100 = platform.request("clk100")
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# Delay software reset by 10us to ensure write has been acked on PCIe.
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rst_delay = WaitTimer(int(10e-6*sys_clk_freq))
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self.submodules += rst_delay
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self.sync += If(self.rst.re, rst_delay.wait.eq(1))
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# PLL
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self.submodules.pll = pll = S7PLL()
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self.comb += pll.reset.eq(rst_delay.done)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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