muselab_icesugar: Modify comments a bit.
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@ -4,8 +4,7 @@
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# Copyright (c) 2021 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# iCESugar FPGA:
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# https://www.aliexpress.com/item/4001201771358.html
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# iCESugar FPGA: https://www.aliexpress.com/item/4001201771358.html
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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@ -55,17 +54,11 @@ _io = [
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# I chose the pin order such that it is the
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# same as on the iCEBreaker so that its PMODs
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# can be reused with this board
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# Pin order similar to iCEBreaker to allow PMODs reuse.
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("PMOD1", "10 6 3 48 9 4 2 47"),
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("PMOD2", "46 44 42 37 45 43 38 36"),
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("PMOD3", "34 31 27 25 32 28 26 23"),
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# numbering similar to the pmods:
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# 0 is marked pin, parallel rows
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# notice that all those pins are also connected to PMOD1
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("J7", "48 - 3 47 - 2"),
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("J7", "48 - 3 47 - 2"), # Numbering similar to PMODS: 0: Marked pin.
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]
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# PMODS --------------------------------------------------------------------------------------------
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@ -73,7 +66,7 @@ _connectors = [
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def led_pmod_io_v11(pmod, offset=0):
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return [
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# LED PMOD: https://www.aliexpress.com/item/1005001504777342.html
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# contrary to the supplied schematic, the two nibbles seem to be swapped on the board
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# Contrary to the supplied schematic, the two nibbles seem to be swapped on the board.
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("user_led_n", offset + 0, Pins(f"{pmod}:4"), IOStandard("LVCMOS33")),
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("user_led_n", offset + 1, Pins(f"{pmod}:5"), IOStandard("LVCMOS33")),
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("user_led_n", offset + 2, Pins(f"{pmod}:6"), IOStandard("LVCMOS33")),
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@ -6,8 +6,7 @@
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# Copyright (c) 2021 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# iCESugar FPGA:
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# https://www.aliexpress.com/item/4001201771358.html
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# iCESugar FPGA: https://www.aliexpress.com/item/4001201771358.html
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import os
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import argparse
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