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orangecrab: combine revisions in target

This commit is contained in:
Greg Davill 2020-03-23 09:20:01 +10:30
parent 357aeac59d
commit eb35ec92ba
3 changed files with 70 additions and 111 deletions
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68
litex_boards/platforms/orangecrab_r0_2.py → litex_boards/platforms/orangecrab.py
View File

@ -6,7 +6,56 @@ from litex.build.lattice import LatticePlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [
_io_r0_1 = [
("clk48", 0, Pins("A9"), IOStandard("LVCMOS33")),
("rgb_led", 0,
Subsignal("r", Pins("V17"), IOStandard("LVCMOS33")),
Subsignal("g", Pins("T17"), IOStandard("LVCMOS33")),
Subsignal("b", Pins("J3"), IOStandard("LVCMOS33")),
),
("ddram", 0,
Subsignal("a", Pins(
"A4 D2 C3 C7 D3 D4 D1 B2",
"C1 A2 A7 C2 C4"),
IOStandard("SSTL135_I")),
Subsignal("ba", Pins("B6 B7 A6"), IOStandard("SSTL135_I")),
Subsignal("ras_n", Pins("C12"), IOStandard("SSTL135_I")),
Subsignal("cas_n", Pins("D13"), IOStandard("SSTL135_I")),
Subsignal("we_n", Pins("B12"), IOStandard("SSTL135_I")),
Subsignal("cs_n", Pins("A12"), IOStandard("SSTL135_I")),
Subsignal("dm", Pins("D16 G16"), IOStandard("SSTL135_I")),
Subsignal("dq", Pins(
"C17 D15 B17 C16 A15 B13 A17 A13",
"F17 F16 G15 F15 J16 C18 H16 F18"),
IOStandard("SSTL135_I"),
Misc("TERMINATION=75")),
Subsignal("dqs_p", Pins("B15 G18"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF DIFFRESISTOR=100")),
Subsignal("clk_p", Pins("J18"), IOStandard("SSTL135D_I")),
Subsignal("cke", Pins("D6"), IOStandard("SSTL135_I")),
Subsignal("odt", Pins("C13"), IOStandard("SSTL135_I")),
Subsignal("reset_n", Pins("B1"), IOStandard("SSTL135_I")),
Misc("SLEWRATE=FAST")
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("U17")),
Subsignal("clk", Pins("U16")),
Subsignal("dq", Pins("U18", "T18", "R18", "N18")),
IOStandard("LVCMOS33")
),
("spi-internal", 0,
Subsignal("cs_n", Pins("B11"), Misc("PULLMODE=UP")),
Subsignal("clk", Pins("C11")),
Subsignal("miso", Pins("A11"), Misc("PULLMODE=UP")),
Subsignal("mosi", Pins("A10"), Misc("PULLMODE=UP")),
IOStandard("LVCMOS33"), Misc("SLEWRATE=SLOW")
),
]
_io_r0_2 = [
("clk48", 0, Pins("A9"), IOStandard("LVCMOS33")),
("rst_n", 0, Pins("V17"), IOStandard("LVCMOS33")),
@ -67,12 +116,19 @@ _io = [
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
_connectors_r0_1 = [
# Feather 0.1" Header Pin Numbers,
# Note: Pin nubering is not continuous.
("GPIO", "N17 M18 C10 C9 - B10 B9 - - C8 B8 A8 H2 J2 N15 R17 N16 - - - - - - - -"),
]
_connectors_r0_2 = [
# Feather 0.1" Header Pin Numbers,
# Note: Pin nubering is not continuous.
("GPIO", "N17 M18 C10 C9 - B10 B9 - - C8 B8 A8 H2 J2 N15 R17 N16 - L4 N3 N4 H4 G4 T17"),
]
# Standard Feather Pins
feather_serial = [
("serial", 0,
@ -103,5 +159,9 @@ class Platform(LatticePlatform):
default_clk_name = "clk48"
default_clk_period = 1e9/48e6
def __init__(self, device='25F', **kwargs):
LatticePlatform.__init__(self, f"LFE5U-{device}-8MG285C", _io, _connectors, **kwargs)
def __init__(self, revision="0.2", device="25F", **kwargs):
assert revision in ["0.1", "0.2"]
self.revision = revision
io = {"0.1": _io_r0_1, "0.2": _io_r0_2 }[revision]
connectors = {"0.1": _connectors_r0_1, "0.2": _connectors_r0_2}[revision]
LatticePlatform.__init__(self, f"LFE5U-{device}-8MG285C", io, connectors, **kwargs)

97
litex_boards/platforms/orangecrab_r0_1.py
View File

@ -1,97 +0,0 @@
# This file is Copyright (c) Greg Davill <greg.davill@gmail.com>
# License: BSD
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk48", 0, Pins("A9"), IOStandard("LVCMOS33")),
("rgb_led", 0,
Subsignal("r", Pins("V17"), IOStandard("LVCMOS33")),
Subsignal("g", Pins("T17"), IOStandard("LVCMOS33")),
Subsignal("b", Pins("J3"), IOStandard("LVCMOS33")),
),
("ddram", 0,
Subsignal("a", Pins(
"A4 D2 C3 C7 D3 D4 D1 B2",
"C1 A2 A7 C2 C4"),
IOStandard("SSTL135_I")),
Subsignal("ba", Pins("B6 B7 A6"), IOStandard("SSTL135_I")),
Subsignal("ras_n", Pins("C12"), IOStandard("SSTL135_I")),
Subsignal("cas_n", Pins("D13"), IOStandard("SSTL135_I")),
Subsignal("we_n", Pins("B12"), IOStandard("SSTL135_I")),
Subsignal("cs_n", Pins("A12"), IOStandard("SSTL135_I")),
Subsignal("dm", Pins("D16 G16"), IOStandard("SSTL135_I")),
Subsignal("dq", Pins(
"C17 D15 B17 C16 A15 B13 A17 A13",
"F17 F16 G15 F15 J16 C18 H16 F18"),
IOStandard("SSTL135_I"),
Misc("TERMINATION=75")),
Subsignal("dqs_p", Pins("B15 G18"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF DIFFRESISTOR=100")),
Subsignal("clk_p", Pins("J18"), IOStandard("SSTL135D_I")),
Subsignal("cke", Pins("D6"), IOStandard("SSTL135_I")),
Subsignal("odt", Pins("C13"), IOStandard("SSTL135_I")),
Subsignal("reset_n", Pins("B1"), IOStandard("SSTL135_I")),
Misc("SLEWRATE=FAST")
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("U17")),
Subsignal("clk", Pins("U16")),
Subsignal("dq", Pins("U18", "T18", "R18", "N18")),
IOStandard("LVCMOS33")
),
("spi-internal", 0,
Subsignal("cs_n", Pins("B11"), Misc("PULLMODE=UP")),
Subsignal("clk", Pins("C11")),
Subsignal("miso", Pins("A11"), Misc("PULLMODE=UP")),
Subsignal("mosi", Pins("A10"), Misc("PULLMODE=UP")),
IOStandard("LVCMOS33"), Misc("SLEWRATE=SLOW")
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
# Feather 0.1" Header Pin Numbers,
# Note: Pin nubering is not continuous.
("GPIO", "N17 M18 C10 C9 - B10 B9 - - C8 B8 A8 H2 J2 N15 R17 N16 - - - - - - - -"),
]
# Standard Feather Pins
feather_serial = [
("serial", 0,
Subsignal("tx", Pins("GPIO:1"), IOStandard("LVCMOS33")),
Subsignal("rx", Pins("GPIO:0"), IOStandard("LVCMOS33"))
)
]
feather_i2c = [
("i2c", 0,
("sda", Pins("GPIO:2"), IOStandard("LVCMOS33")),
("scl", Pins("GPIO:3"), IOStandard("LVCMOS33"))
)
]
feather_spi = [
("spi",0,
("miso", Pins("GPIO:14"), IOStandard("LVCMOS33")),
("mosi", Pins("GPIO:16"), IOStandard("LVCMOS33")),
("sck", Pins("GPIO:15"), IOStandard("LVCMOS33"))
)
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk48"
default_clk_period = 1e9/48e6
def __init__(self, device='25F', **kwargs):
LatticePlatform.__init__(self, f"LFE5U-{device}-8MG285C", _io, _connectors, **kwargs)

16
litex_boards/targets/orangecrab.py
View File

@ -8,7 +8,7 @@ import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import orangecrab_r0_1, orangecrab_r0_2
from litex_boards.platforms import orangecrab
from litex.build.lattice.trellis import trellis_args, trellis_argdict
@ -77,13 +77,9 @@ class _CRG(Module):
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs):
# Board Revision ---------------------------------------------------------------------------
revision = kwargs.get("revision", "r0.2")
boards = {
'r0.1': orangecrab_r0_1,
'r0.2': orangecrab_r0_2
}
orangecrab = boards.get(revision)
platform = orangecrab.Platform(toolchain=toolchain)
revision = kwargs.get("revision", "0.2")
device = kwargs.get("device", "25F")
platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain)
# Serial -----------------------------------------------------------------------------------
platform.add_extension(orangecrab.feather_serial)
@ -133,8 +129,8 @@ def main():
trellis_args(parser)
parser.add_argument("--sys-clk-freq", default=48e6,
help="system clock frequency (default=48MHz)")
parser.add_argument("--revision", default="r0.2",
help="Board Revision {r0.1, r0.2} (default=r0.2)")
parser.add_argument("--revision", default="0.2",
help="Board Revision {0.1, 0.2} (default=0.2)")
parser.add_argument("--device", default="25F",
help="ECP5 device (default=25F)")
parser.add_argument("--sdram-device", default="MT41K64M16",