mirror of
https://github.com/litex-hub/litex-boards.git
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partner: aller/nereid/tagus fix copyright (Rohit Singh as main author), do some cosmetic
This commit is contained in:
Florent Kermarrec
parent
5b605d37a2
commit
ec5540454b
6 changed files with 34 additions and 61 deletions
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@ -1,5 +1,5 @@
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# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from litex.build.generic_platform import *
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@ -1,5 +1,5 @@
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# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from litex.build.generic_platform import *
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@ -1,5 +1,5 @@
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# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
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# This file is Copyright (c) 2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from litex.build.generic_platform import *
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@ -1,7 +1,7 @@
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#!/usr/bin/env python3
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# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import sys
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@ -55,9 +55,6 @@ class AllerSoC(SoCSDRAM):
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def __init__(self, platform, with_pcie_uart=True):
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sys_clk_freq = int(100e6)
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# soc sdram
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# ------------------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, sys_clk_freq,
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csr_data_width=32,
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integrated_rom_size=0x10000,
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@ -66,23 +63,19 @@ class AllerSoC(SoCSDRAM):
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ident="Aller LiteX Test SoC", ident_version=True,
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with_uart=not with_pcie_uart)
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# crg
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# ------------------------------------------------------------------------------------------
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform, sys_clk_freq)
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self.add_csr("crg")
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# dna
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# ------------------------------------------------------------------------------------------
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# DNA --------------------------------------------------------------------------------------
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self.submodules.dna = dna.DNA()
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self.add_csr("dna")
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# xadc
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# ------------------------------------------------------------------------------------------
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# XADC -------------------------------------------------------------------------------------
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self.submodules.xadc = xadc.XADC()
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self.add_csr("xadc")
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# sdram
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# ------------------------------------------------------------------------------------------
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# SDRAM ------------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
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platform.request("ddram"),
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@ -94,8 +87,7 @@ class AllerSoC(SoCSDRAM):
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sdram_module.timing_settings)
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self.add_csr("ddrphy")
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# pcie
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# ------------------------------------------------------------------------------------------
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# PCIe -------------------------------------------------------------------------------------
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# pcie phy
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000)
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self.pcie_phy.cd_pcie.clk.attr.add("keep")
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@ -109,7 +101,8 @@ class AllerSoC(SoCSDRAM):
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self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
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# pcie wishbone bridge
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self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=self.shadow_base)
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self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
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lambda a: 1, shadow_base=self.shadow_base)
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self.add_wb_master(self.pcie_wishbone.wishbone)
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# pcie dma
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@ -130,7 +123,6 @@ class AllerSoC(SoCSDRAM):
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self.add_constant(k + "_INTERRUPT", i)
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# pcie_uart
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# ------------------------------------------------------------------------------------------
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if with_pcie_uart:
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class PCIeUART(Module, AutoCSR):
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def __init__(self, uart):
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@ -171,8 +163,7 @@ class AllerSoC(SoCSDRAM):
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self.submodules.pcie_uart = PCIeUART(uart_interface)
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self.add_csr("pcie_uart")
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# leds
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# ------------------------------------------------------------------------------------------
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# Leds -------------------------------------------------------------------------------------
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# led blinking (sys)
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sys_counter = Signal(32)
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self.sync.sys += sys_counter.eq(sys_counter + 1)
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@ -1,7 +1,7 @@
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#!/usr/bin/env python3
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# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import sys
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@ -28,8 +28,7 @@ from litepcie.frontend.wishbone import LitePCIeWishboneBridge
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from litex_boards.platforms import nereid
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# sdram module
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# --------------------------------------------------------------------------------------------------
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# SDRAM Module -------------------------------------------------------------------------------------
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class MT8KTF51264(SDRAMModule):
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memtype = "DDR3"
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@ -65,7 +64,7 @@ class CRG(Module):
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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# NereidSoC ------------------------------------------------------------------------------------------
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# NereidSoC ----------------------------------------------------------------------------------------
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class NereidSoC(SoCSDRAM):
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SoCSDRAM.mem_map["csr"] = 0x00000000
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@ -73,9 +72,6 @@ class NereidSoC(SoCSDRAM):
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def __init__(self, platform, with_pcie_uart=True):
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sys_clk_freq = int(100e6)
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# soc sdram
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# ------------------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, sys_clk_freq,
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csr_data_width=32,
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integrated_rom_size=0x10000,
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@ -84,23 +80,19 @@ class NereidSoC(SoCSDRAM):
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ident="Nereid LiteX Test SoC", ident_version=True,
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with_uart=not with_pcie_uart)
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# crg
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# ------------------------------------------------------------------------------------------
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform, sys_clk_freq)
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self.add_csr("crg")
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# dna
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# ------------------------------------------------------------------------------------------
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# DNA --------------------------------------------------------------------------------------
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self.submodules.dna = dna.DNA()
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self.add_csr("dna")
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# xadc
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# ------------------------------------------------------------------------------------------
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# XADC -------------------------------------------------------------------------------------
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self.submodules.xadc = xadc.XADC()
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self.add_csr("xadc")
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# sdram
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# ------------------------------------------------------------------------------------------
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# SDRAM ------------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
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platform.request("ddram"),
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@ -112,8 +104,7 @@ class NereidSoC(SoCSDRAM):
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sdram_module.timing_settings)
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self.add_csr("ddrphy")
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# pcie
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# ------------------------------------------------------------------------------------------
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# PCIe -------------------------------------------------------------------------------------
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# pcie phy
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000)
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self.pcie_phy.cd_pcie.clk.attr.add("keep")
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@ -127,7 +118,8 @@ class NereidSoC(SoCSDRAM):
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self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
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# pcie wishbone bridge
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self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=self.shadow_base)
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self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
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lambda a: 1, shadow_base=self.shadow_base)
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self.add_wb_master(self.pcie_wishbone.wishbone)
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# pcie dma
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@ -147,8 +139,7 @@ class NereidSoC(SoCSDRAM):
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self.comb += self.pcie_msi.irqs[i].eq(v)
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self.add_constant(k + "_INTERRUPT", i)
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# pcie_uart
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# ------------------------------------------------------------------------------------------
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# pcie uart
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if with_pcie_uart:
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class PCIeUART(Module, AutoCSR):
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def __init__(self, uart):
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@ -189,8 +180,7 @@ class NereidSoC(SoCSDRAM):
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self.submodules.pcie_uart = PCIeUART(uart_interface)
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self.add_csr("pcie_uart")
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# leds
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# ------------------------------------------------------------------------------------------
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# Leds -------------------------------------------------------------------------------------
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# led blinking (sys)
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sys_counter = Signal(32)
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self.sync.sys += sys_counter.eq(sys_counter + 1)
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@ -1,7 +1,8 @@
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#!/usr/bin/env python3
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# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import sys
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@ -56,9 +57,6 @@ class TagusSoC(SoCSDRAM):
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def __init__(self, platform, with_pcie_uart=True):
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sys_clk_freq = int(100e6)
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# soc sdram
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# ------------------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, sys_clk_freq,
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csr_data_width=32,
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integrated_rom_size=0x10000,
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@ -67,23 +65,19 @@ class TagusSoC(SoCSDRAM):
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ident="Tagus LiteX Test SoC", ident_version=True,
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with_uart=not with_pcie_uart)
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# crg
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# ------------------------------------------------------------------------------------------
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform, sys_clk_freq)
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self.add_csr("crg")
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# dna
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# ------------------------------------------------------------------------------------------
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# DNA --------------------------------------------------------------------------------------
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self.submodules.dna = dna.DNA()
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self.add_csr("dna")
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# xadc
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# ------------------------------------------------------------------------------------------
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# XADC -------------------------------------------------------------------------------------
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self.submodules.xadc = xadc.XADC()
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self.add_csr("xadc")
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# sdram
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# ------------------------------------------------------------------------------------------
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# SDRAM ------------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
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platform.request("ddram"),
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@ -95,8 +89,7 @@ class TagusSoC(SoCSDRAM):
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sdram_module.timing_settings)
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self.add_csr("ddrphy")
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# pcie
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# ------------------------------------------------------------------------------------------
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# PCIe -------------------------------------------------------------------------------------
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# pcie phy
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000)
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self.pcie_phy.cd_pcie.clk.attr.add("keep")
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@ -110,7 +103,8 @@ class TagusSoC(SoCSDRAM):
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self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
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# pcie wishbone bridge
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self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=self.shadow_base)
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self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
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lambda a: 1, shadow_base=self.shadow_base)
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self.add_wb_master(self.pcie_wishbone.wishbone)
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# pcie dma
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@ -131,7 +125,6 @@ class TagusSoC(SoCSDRAM):
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self.add_constant(k + "_INTERRUPT", i)
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# pcie_uart
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# ------------------------------------------------------------------------------------------
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if with_pcie_uart:
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class PCIeUART(Module, AutoCSR):
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def __init__(self, uart):
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@ -172,8 +165,7 @@ class TagusSoC(SoCSDRAM):
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self.submodules.pcie_uart = PCIeUART(uart_interface)
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self.add_csr("pcie_uart")
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# leds
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# ------------------------------------------------------------------------------------------
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# Leds -------------------------------------------------------------------------------------
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# led blinking (sys)
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sys_counter = Signal(32)
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self.sync.sys += sys_counter.eq(sys_counter + 1)
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