mimas_v7: cleanup, make it similar to others boards
This commit is contained in:
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54f39b600a
commit
eca9bf10ae
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@ -35,44 +35,39 @@ _io = [
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("cpu_reset", 0, Pins("M2"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("M2"), IOStandard("LVCMOS33")),
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# Not usable unless EEPROM is reprogrammed to set Channel A of FT2232H to ASYNC Serial (UART) mode
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("serial", 0, # Can be used when FT2232H's Channel A configured to ASYNC Serial (UART) mode
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# ("serial", 0,
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Subsignal("tx", Pins("Y21")),
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# Subsignal("tx", Pins("Y22")),
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Subsignal("rx", Pins("Y22")),
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# Subsignal("rx", Pins("Y21")),
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IOStandard("LVCMOS33")
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# IOStandard("LVCMOS33")
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),
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# ),
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# Not usable unless EEPROM is reprogrammed to set Channel A of FT2232H to ASYNC FIFO 245 mode
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("usb_fifo", 0, # Can be used when FT2232H's Channel A configured to ASYNC FIFO 245 mode
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# Host can interface with this as if it were UART--See issue https://github.com/enjoy-digital/litex/issues/231 for more info
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Subsignal("data", Pins("Y22 Y21 AB22 AA21 AB21 AA20 AB20 AA18")),
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("usb_fifo", 0,
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Subsignal("data", Pins("Y22 Y21 AB22 AA21 AB21 AA20 AB20 AA18")),
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Subsignal("rxf_n", Pins("W21")),
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Subsignal("rxf_n", Pins("W21")),
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Subsignal("txe_n", Pins("V22")),
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Subsignal("txe_n", Pins("V22")),
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Subsignal("rd_n", Pins("AA19")),
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Subsignal("rd_n", Pins("AA19")),
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Subsignal("wr_n", Pins("W22")),
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Subsignal("wr_n", Pins("W22")),
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Subsignal("siwua", Pins("U21")),
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Subsignal("siwua", Pins("U21")),
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Subsignal("oe_n", Pins("T21")),
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Subsignal("oe_n", Pins("T21")),
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IOStandard("LVCMOS33"), Drive(8), Misc("SLEW=FAST")
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IOStandard("LVCMOS33"), Drive(8), Misc("SLEW=FAST")
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),
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),
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("spiflash4x", 0,
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("T19")),
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Subsignal("cs_n", Pins("T19")),
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Subsignal("clk", Pins("L12")),
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Subsignal("clk", Pins("L12")),
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Subsignal("dq", Pins("P22", "R22", "P21", "R21")),
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Subsignal("dq", Pins("P22", "R22", "P21", "R21")),
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IOStandard("LVCMOS33")
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IOStandard("LVCMOS33")
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),
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),
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("spiflash", 0,
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("spiflash", 0,
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Subsignal("cs_n", Pins("T19")),
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Subsignal("cs_n", Pins("T19")),
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Subsignal("clk", Pins("L12")),
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Subsignal("clk", Pins("L12")),
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Subsignal("mosi", Pins("P22")),
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Subsignal("mosi", Pins("P22")),
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Subsignal("miso", Pins("R22")),
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Subsignal("miso", Pins("R22")),
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Subsignal("wp", Pins("P21")),
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Subsignal("wp", Pins("P21")),
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Subsignal("hold", Pins("R21")),
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Subsignal("hold", Pins("R21")),
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IOStandard("LVCMOS33"),
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IOStandard("LVCMOS33"),
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),
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),
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# DDR3 MT41J128M16XX-125
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# freq: 400MHz, data width: 16
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("ddram", 0,
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("ddram", 0,
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Subsignal("a", Pins(
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Subsignal("a", Pins(
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"U6 T5 Y6 T6 V2 T4 Y2 R2",
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"U6 T5 Y6 T6 V2 T4 Y2 R2",
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@ -82,48 +77,43 @@ _io = [
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Subsignal("ras_n", Pins("V5"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("V5"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("T1"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("T1"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("R3"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("R3"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("T3"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("Y7 AA1"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("Y7 AA1"), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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Subsignal("dq", Pins(
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"Y8 AB6 W9 AA8 AB7 V7 AB8 W7",
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"Y8 AB6 W9 AA8 AB7 V7 AB8 W7",
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"V4 AB2 AA5 AB3 AB5 W4 AB1 AA4"),
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"V4 AB2 AA5 AB3 AB5 W4 AB1 AA4"),
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IOStandard("SSTL15")),
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IOStandard("SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins("V9 Y3"), IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_p", Pins("V9 Y3"), IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("V8 AA3"), IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("V8 AA3"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("U3"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("U3"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("V3"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("V3"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("U1"), IOStandard("SSTL15")),
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Subsignal("cke", Pins("U1"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("W2"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("W2"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("T3"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("U7"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("U7"), IOStandard("SSTL15")),
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Misc("SLEW=FAST"),
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Misc("SLEW=FAST"),
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),
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),
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# Seven Seg display not yet mapped here
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# 24AA02E48T EEPROM
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("eeprom", 0,
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("eeprom", 0,
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Subsignal("scl", Pins("N5")),
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Subsignal("scl", Pins("N5")),
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Subsignal("sda", Pins("P6")),
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Subsignal("sda", Pins("P6")),
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IOStandard("LVCMOS33")
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IOStandard("LVCMOS33")
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),
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),
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# Micro SD not yet mapped here
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# FIXME not sure how to map ethernet. Is this RGMII?
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("eth_clocks", 0,
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("eth_clocks", 0,
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Subsignal("tx", Pins("U20")),
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Subsignal("tx", Pins("U20")),
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Subsignal("rx", Pins("W19")),
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Subsignal("rx", Pins("W19")),
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IOStandard("LVCMOS33")
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IOStandard("LVCMOS33")
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),
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),
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("eth", 0,
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("eth", 0,
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Subsignal("rst_n", Pins("R14")),
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Subsignal("rst_n", Pins("R14"), IOStandard("LVCMOS33")),
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# Subsignal("int_n", Pins("Y14")), # usually RGMII has the int_n pin
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Subsignal("int_n", Pins("V19")),
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Subsignal("mdio", Pins("P16"), Misc("SLEW=FAST")),
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Subsignal("mdio", Pins("P16")),
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Subsignal("mdc", Pins("R19"), Misc("SLEW=FAST")),
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Subsignal("mdc", Pins("R19")),
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Subsignal("rx_ctl", Pins("Y19")),
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Subsignal("rx_ctl", Pins("Y19")),
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Subsignal("rx_data", Pins("AB18 W20 W17 V20")),
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Subsignal("rx_data", Pins("AB18 W20 W17 V20")),
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Subsignal("tx_ctl", Pins("T20"), Misc("SLEW=FAST")),
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Subsignal("tx_ctl", Pins("T20")),
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Subsignal("tx_data", Pins("V18 U18 V17 U17"), Misc("SLEW=FAST")),
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Subsignal("tx_data", Pins("V18 U18 V17 U17")),
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IOStandard("LVCMOS33")
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IOStandard("LVCMOS33")
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),
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),
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@ -138,9 +128,9 @@ _io = [
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Subsignal("data2_n", Pins("N2"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("N2"), IOStandard("TMDS_33")),
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Subsignal("scl", Pins("J2"), IOStandard("LVCMOS33")),
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Subsignal("scl", Pins("J2"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("H2"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("H2"), IOStandard("LVCMOS33")),
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Subsignal("hpd_en", Pins("G2"), IOStandard("LVCMOS33")), # FIXME not sure if this is the hdmi_rx_hpa pin
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Subsignal("hpd_en", Pins("G2"), IOStandard("LVCMOS33")),
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Subsignal("cec", Pins("K2"), IOStandard("LVCMOS33")),
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Subsignal("cec", Pins("K2"), IOStandard("LVCMOS33")), # FIXME
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# Subsignal("txen", Pins("R3"), IOStandard("LVCMOS33")), # not sure if we need this
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# Subsignal("txen", Pins("R3"), IOStandard("LVCMOS33")), # FIXME
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),
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),
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("hdmi_out", 0,
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("hdmi_out", 0,
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@ -154,11 +144,9 @@ _io = [
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Subsignal("data2_n", Pins("F1"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("F1"), IOStandard("TMDS_33")),
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Subsignal("scl", Pins("D2"), IOStandard("LVCMOS33")),
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Subsignal("scl", Pins("D2"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("C2"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("C2"), IOStandard("LVCMOS33")),
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Subsignal("cec", Pins("E2"), IOStandard("LVCMOS33")),
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Subsignal("cec", Pins("E2"), IOStandard("LVCMOS33")), # FIXME
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Subsignal("hdp", Pins("B2"), IOStandard("LVCMOS25")), # FIXME should this be hpd?
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Subsignal("hdp", Pins("B2"), IOStandard("LVCMOS33")), # FIXME
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),
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),
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# Mini display ports not yet mapped here
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]
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]
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# Connectors ---------------------------------------------------------------------------------------
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# Connectors ---------------------------------------------------------------------------------------
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@ -174,11 +162,8 @@ class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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default_clk_period = 1e9/100e6
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def __init__(self, variant="50t"):
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def __init__(self):
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device = {
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XilinxPlatform.__init__(self, "xc7a50tfgg484-1", _io, _connectors, toolchain="vivado")
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"50t": "xc7a50tfgg484-1"
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}[variant]
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XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado")
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self.toolchain.bitstream_commands = \
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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self.toolchain.additional_commands = \
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@ -42,19 +42,14 @@ class _CRG(Module):
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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# BaseSoC ------------------------------------------------------------------------------------------
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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class BaseSoC(SoCSDRAM):
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def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, uart_name="usb_fifo", **kwargs):
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def __init__(self, sys_clk_freq=int(100e6), **kwargs):
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platform = mimas_a7.Platform()
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platform = mimas_a7.Platform()
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# SoCSDRAM ---------------------------------------------------------------------------------
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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integrated_rom_size=integrated_rom_size,
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integrated_sram_size=0x8000,
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uart_name=uart_name,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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@ -80,18 +75,22 @@ class EthernetSoC(BaseSoC):
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mem_map.update(BaseSoC.mem_map)
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, **kwargs):
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def __init__(self, **kwargs):
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BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
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BaseSoC.__init__(self, **kwargs)
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self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
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# Ethernet ---------------------------------------------------------------------------------
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self.platform.request("eth"))
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# phy
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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self.add_csr("ethphy")
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self.add_csr("ethphy")
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# mac
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
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interface="wishbone", endianness=self.cpu.endianness)
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interface="wishbone", endianness=self.cpu.endianness)
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self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
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self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
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self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
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self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
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self.add_csr("ethmac")
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self.add_csr("ethmac")
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self.add_interrupt("ethmac")
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self.add_interrupt("ethmac")
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# timing constraints
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
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self.platform.add_false_path_constraints(
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self.platform.add_false_path_constraints(
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@ -99,7 +98,6 @@ class EthernetSoC(BaseSoC):
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self.ethphy.crg.cd_eth_rx.clk,
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self.ethphy.crg.cd_eth_rx.clk,
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self.ethphy.crg.cd_eth_tx.clk)
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self.ethphy.crg.cd_eth_tx.clk)
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# Build --------------------------------------------------------------------------------------------
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# Build --------------------------------------------------------------------------------------------
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def main():
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def main():
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@ -107,10 +105,8 @@ def main():
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builder_args(parser)
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builder_args(parser)
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soc_sdram_args(parser)
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soc_sdram_args(parser)
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vivado_build_args(parser)
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vivado_build_args(parser)
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parser.add_argument("--with-ethernet", action="store_true",
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parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support")
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help="enable Ethernet support")
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args = parser.parse_args()
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args = parser.parse_args()
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cls = EthernetSoC if args.with_ethernet else BaseSoC
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cls = EthernetSoC if args.with_ethernet else BaseSoC
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soc = cls(**soc_sdram_argdict(args))
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soc = cls(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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