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targets/arty: add fixed sdcard clock and remove sys2x (use NETWORKING interface_type on DDR3).

This commit is contained in:
Florent Kermarrec 2020-06-25 11:21:24 +02:00
parent 6753a92296
commit efe33c9764
1 changed files with 3 additions and 4 deletions
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7
litex_boards/targets/arty.py
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@ -27,11 +27,11 @@ from liteeth.phy.mii import LiteEthPHYMII
class _CRG(Module): class _CRG(Module):
def __init__(self, platform, sys_clk_freq): def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_eth = ClockDomain() self.clock_domains.cd_eth = ClockDomain()
self.clock_domains.cd_sdcard = ClockDomain()
# # # # # #
@ -39,11 +39,11 @@ class _CRG(Module):
self.comb += pll.reset.eq(~platform.request("cpu_reset")) self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk100"), 100e6) pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6) pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_eth, 25e6) pll.create_clkout(self.cd_eth, 25e6)
pll.create_clkout(self.cd_sdcard, 10e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
@ -66,8 +66,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3", memtype = "DDR3",
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq)
interface_type = "MEMORY")
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,