initial support for machdyne konfekt and noir

README.md

@@ -167,6 +167,8 @@ Some of the suported boards, see yours? Give LiteX-Boards a try!
     ├── logicbone
     ├── machdyne_krote
     ├── machdyne_schoko
+    ├── machdyne_konfekt
+    ├── machdyne_noir
     ├── marblemini
     ├── marble
     ├── micronova_mercury2

litex_boards/platforms/machdyne_konfekt.py

@@ -0,0 +1,153 @@
+#
+# This file is part of LiteX-Boards.
+#
+# Copright (c) 2022 Lone Dynamics Corporation <info@lonedynamics.com>
+#
+# SPDX-License-Identifier: BSD-2-Clause
+
+from litex.build.generic_platform import *
+from litex.build.lattice import LatticePlatform
+from litex.build.openfpgaloader import OpenFPGALoader
+
+# IOs ----------------------------------------------------------------------------------------------
+
+_io_vx = [
+
+    # Clock
+    ("clk48", 0,  Pins("A7"),  IOStandard("LVCMOS33")),
+
+    # Leds
+    ("user_led", 0, Pins("G1"), IOStandard("LVCMOS33")),
+    ("user_led", 1, Pins("E1"), IOStandard("LVCMOS33")),
+    ("user_led", 2, Pins("C1"),  IOStandard("LVCMOS33")),
+
+    ("rgb_led", 0,
+        Subsignal("r", Pins("G1"), IOStandard("LVCMOS33")),
+        Subsignal("g", Pins("E1"), IOStandard("LVCMOS33")),
+        Subsignal("b", Pins("C1"),  IOStandard("LVCMOS33")),
+    ),
+
+    # Buttons
+    ("usr_btn", 0, Pins("K1"), IOStandard("LVCMOS33")),
+
+    # SDRAM
+    ("sdram_clock", 0, Pins("F16"), IOStandard("LVTTL33")),
+    ("sdram", 0,
+        Subsignal("a", Pins(
+            "M13 M14 L14 L13 G12 G13 G14 G15",
+            "F12 F13 T15 F14 E14")),
+        Subsignal("ba",    Pins("P14 N13")),
+        Subsignal("cs_n",  Pins("G16")),
+        Subsignal("cke",   Pins("F15")),
+        Subsignal("ras_n", Pins("J16")),
+        Subsignal("cas_n", Pins("K16")),
+        Subsignal("we_n",  Pins("L15")),
+        Subsignal("dq", Pins(
+            "R15 R16 P16 P15 N16 N14 M16 M15",
+            "E15 D16 D14 C16 B16 C14 C15 B15")),
+        Subsignal("dm", Pins("L16 E16")),
+        IOStandard("LVTTL33")
+    ),
+
+    # Differential Data Multiple Interface
+    ("ddmi", 0,
+        Subsignal("clk_p",    Pins("M1"),
+            IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
+        Subsignal("data0_p",  Pins("P1"),
+            IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
+        Subsignal("data1_p",  Pins("R2"),
+            IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
+        Subsignal("data2_p",  Pins("R5"),
+            IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
+    ),
+
+    # USB-C
+    ("usb", 0,
+        Subsignal("d_p", Pins("T6")),
+        Subsignal("d_n", Pins("R6")),
+        Subsignal("pullup", Pins("R7")),
+        IOStandard("LVCMOS33")
+    ),
+
+    # USB HOST
+    ("usb_host", 0,
+        Subsignal("dp", Pins("B1")),
+        Subsignal("dm", Pins("B2")),
+        IOStandard("LVCMOS33")
+    ),
+
+    # 3.5MM AUDIO
+    ("audio_pwm", 0,
+        Subsignal("left", Pins("M11")),
+        Subsignal("right", Pins("P12")),
+        IOStandard("LVCMOS33")
+    ),
+
+    # 3.5MM VIDEO
+    ("video_dac", 0,
+        Subsignal("data", Pins("T13 R12 T14 R13")),
+        IOStandard("LVCMOS33")
+    ),
+
+    # DEBUG UART
+    ("serial", 0,
+        Subsignal("tx", Pins("J2")),
+        Subsignal("rx", Pins("J1")),
+        IOStandard("LVCMOS33")
+    ),
+]
+
+_io_v0 = [
+
+    # SD card w/ SD-mode interface
+    ("sdcard", 0,
+    #    Subsignal("cd", Pins("A5")),
+        Subsignal("clk", Pins("B4")),
+        Subsignal("cmd", Pins("A3")),
+        Subsignal("data", Pins("A4 B5 A2 B3")),
+        Misc("SLEWRATE=FAST"),
+        IOStandard("LVCMOS33")
+    ),
+
+    # SD card w/ SPI interface
+    ("spisdcard", 0,
+        Subsignal("clk",  Pins("B4")),
+        Subsignal("mosi", Pins("A3")),
+        Subsignal("cs_n", Pins("B3")),
+        Subsignal("miso", Pins("A4")),
+        Misc("SLEWRATE=FAST"),
+        IOStandard("LVCMOS33"),
+    ),
+
+]
+
+# Connectors ---------------------------------------------------------------------------------------
+
+_connectors_vx = [
+
+]
+
+# Platform -----------------------------------------------------------------------------------------
+
+class Platform(LatticePlatform):
+    default_clk_name   = "clk48"
+    default_clk_period = 1e9/48e6
+
+    def __init__(self, revision="v0", device="12F", toolchain="trellis", **kwargs):
+        assert revision in ["v0"]
+        assert device in ["12F", "25F", "45F", "85F"]
+        self.revision = revision
+
+        io = _io_vx
+        connectors = _connectors_vx
+
+        if revision == "v0": io += _io_v0
+
+        LatticePlatform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
+
+    def create_programmer(self, cable):
+        return OpenFPGALoader(cable=cable)
+
+    def do_finalize(self, fragment):
+        LatticePlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)

litex_boards/platforms/machdyne_noir.py

@@ -0,0 +1,159 @@
+#
+# This file is part of LiteX-Boards.
+#
+# Copright (c) 2022 Lone Dynamics Corporation <info@lonedynamics.com>
+#
+# SPDX-License-Identifier: BSD-2-Clause
+
+from litex.build.generic_platform import *
+from litex.build.lattice import LatticePlatform
+from litex.build.openfpgaloader import OpenFPGALoader
+
+# IOs ----------------------------------------------------------------------------------------------
+
+_io_vx = [
+
+    # Clock
+    ("clk48", 0,  Pins("A7"),  IOStandard("LVCMOS33")),
+
+    # Leds
+    ("user_led", 0, Pins("C1"), IOStandard("LVCMOS33")),
+    ("user_led", 1, Pins("E1"), IOStandard("LVCMOS33")),
+    ("user_led", 2, Pins("G1"),  IOStandard("LVCMOS33")),
+    ("rgb_led", 0,
+        Subsignal("r", Pins("C1"), IOStandard("LVCMOS33")),
+        Subsignal("g", Pins("E1"), IOStandard("LVCMOS33")),
+        Subsignal("b", Pins("G1"),  IOStandard("LVCMOS33")),
+    ),
+
+    # DDR3L
+    ("ddram", 0,
+        Subsignal("a", Pins(
+            "R15 L13 P14 R14 L12 T14 N11 T13",
+            "P12 T15 C14 M13 E14 R13 M14 D14"),
+            IOStandard("SSTL135_I")),
+        Subsignal("ba",    Pins("N16 K13 P16"), IOStandard("SSTL135_I")),
+        Subsignal("ras_n", Pins("L16"),  IOStandard("SSTL135_I")),
+        Subsignal("cas_n", Pins("M16"),  IOStandard("SSTL135_I")),
+        Subsignal("we_n",  Pins("P15"),  IOStandard("SSTL135_I")),
+        Subsignal("cs_n",  Pins("M15"),  IOStandard("SSTL135_I")),
+        Subsignal("dm", Pins("F13 J13"), IOStandard("SSTL135_I")),
+        Subsignal("dq", Pins(
+            "F14 E16 F12 F15 G13 B16 G12 B15",
+            "J14 J16 K15 K14 H14 K16 H13 J15"),
+            IOStandard("SSTL135_I"),
+            Misc("TERMINATION=75")),
+        Subsignal("dqs_p", Pins("D16 G16"), IOStandard("SSTL135D_I"),
+            Misc("TERMINATION=OFF DIFFRESISTOR=100")),
+        Subsignal("clk_p", Pins("C16"), IOStandard("SSTL135D_I")),
+        Subsignal("cke",   Pins("K12"),  IOStandard("SSTL135_I")),
+        Subsignal("odt",   Pins("L15"), IOStandard("SSTL135_I")),
+        Subsignal("reset_n", Pins("R12"), IOStandard("SSTL135_I")),
+        Misc("SLEWRATE=FAST")
+    ),
+
+    # Differential Data Multiple Interface
+    ("ddmi", 0,
+        Subsignal("clk_p",    Pins("M1"),
+            IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
+        Subsignal("data0_p",  Pins("P1"),
+            IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
+        Subsignal("data1_p",  Pins("R2"),
+            IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
+        Subsignal("data2_p",  Pins("R5"),
+            IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
+    ),
+
+    # USB-C
+    ("usb", 0,
+        Subsignal("d_p", Pins("T6")),
+        Subsignal("d_n", Pins("R6")),
+        Subsignal("pullup", Pins("R7")),
+        IOStandard("LVCMOS33")
+    ),
+
+    # USB HOST
+    ("usb_host", 0,
+        Subsignal("dp", Pins("B1")),
+        Subsignal("dm", Pins("B2")),
+        IOStandard("LVCMOS33")
+    ),
+
+    # 3.5MM AUDIO
+    ("audio_pwm", 0,
+        Subsignal("left", Pins("N7")),
+        Subsignal("right", Pins("M7")),
+        IOStandard("LVCMOS33")
+    ),
+
+    # DEBUG UART
+    ("serial", 0,
+        Subsignal("tx", Pins("J2")),
+        Subsignal("rx", Pins("J1")),
+        IOStandard("LVCMOS33")
+    ),
+
+    # SPI
+    ("spiflash", 0,
+        Subsignal("cs_n",   Pins("N8")),
+        Subsignal("miso",   Pins("T7")),
+        Subsignal("mosi",   Pins("T8")),
+        Misc("SLEWRATE=FAST"),
+        IOStandard("LVCMOS33"),
+    ),
+
+]
+
+_io_v0 = [
+
+    # SD card w/ SD-mode interface
+    ("sdcard", 0,
+        Subsignal("cd", Pins("A5")),
+        Subsignal("clk", Pins("B4")),
+        Subsignal("cmd", Pins("A3")),
+        Subsignal("data", Pins("A4 B5 A2 B3")),
+        Misc("SLEWRATE=FAST"),
+        IOStandard("LVCMOS33")
+    ),
+
+    # SD card w/ SPI interface
+    ("spisdcard", 0,
+        Subsignal("clk",  Pins("B4")),
+        Subsignal("mosi", Pins("A3")),
+        Subsignal("cs_n", Pins("B3")),
+        Subsignal("miso", Pins("A4")),
+        Misc("SLEWRATE=FAST"),
+        IOStandard("LVCMOS33"),
+    ),
+
+]
+
+# Connectors ---------------------------------------------------------------------------------------
+
+_connectors_vx = [
+]
+
+# Platform -----------------------------------------------------------------------------------------
+
+class Platform(LatticePlatform):
+    default_clk_name   = "clk48"
+    default_clk_period = 1e9/48e6
+
+    def __init__(self, revision="v0", device="45F", toolchain="trellis", **kwargs):
+        assert revision in ["v0"]
+        assert device in ["12F", "25F", "45F", "85F"]
+        self.revision = revision
+
+        io = _io_vx
+        connectors = _connectors_vx
+
+        if revision == "v0": io += _io_v0
+
+        LatticePlatform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
+
+    def create_programmer(self, cable):
+        return OpenFPGALoader(cable=cable)
+
+    def do_finalize(self, fragment):
+        LatticePlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)

litex_boards/targets/machdyne_konfekt.py

@@ -0,0 +1,227 @@
+#!/usr/bin/env python3
+
+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) Lone Dynamics Corporation <info@lonedynamics.com>
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+
+import os
+import sys
+import json
+
+from migen import *
+from litex_boards.platforms import machdyne_konfekt
+
+from litex.build.lattice.trellis import trellis_args, trellis_argdict
+from litex.build.io import DDROutput
+
+from litex.soc.cores.clock import *
+from litex.soc.cores.led import LedChaser
+from litex.soc.cores.usb_ohci import USBOHCI
+from litex.soc.cores.video import VideoVGAPHY
+from litex.soc.cores.video import VideoHDMIPHY
+
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.builder import *
+
+from litedram.modules import W9825G6KH6
+from litedram.modules import IS42S16320
+
+from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
+from litedram.phy import QuarterRateGENSDRPHY
+
+from litex.soc.integration.soc import SoCRegion
+
+# CRG ---------------------------------------------------------------------------------------------
+
+class _CRG(Module):
+    def __init__(self, platform, sys_clk_freq, sdram_rate):
+        self.rst = Signal()
+        self.clock_domains.cd_por = ClockDomain()
+        self.clock_domains.cd_sys = ClockDomain()
+        self.clock_domains.cd_video = ClockDomain()
+        self.clock_domains.cd_video5x = ClockDomain()
+
+        # Clk / Rst
+        clk48 = platform.request("clk48")
+
+        # Power on reset
+        por_count = Signal(16, reset=2**16-1)
+        por_done  = Signal()
+        self.comb += self.cd_por.clk.eq(clk48)
+        self.comb += por_done.eq(por_count == 0)
+        self.sync.por += If(~por_done, por_count.eq(por_count - 1))
+
+        # PLL
+        self.submodules.pll = pll = ECP5PLL()
+        self.comb += pll.reset.eq(~por_done | self.rst)
+        pll.register_clkin(clk48, 48e6)
+        pll.create_clkout(self.cd_sys, sys_clk_freq)
+
+        if sdram_rate == "1:2":
+            self.clock_domains.cd_sys2x = ClockDomain()
+            self.clock_domains.cd_sys2x_ps = ClockDomain()
+            pll.create_clkout(self.cd_sys2x,    2*sys_clk_freq)
+            pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180)
+        elif sdram_rate == "1:4":
+            self.clock_domains.cd_sys2x = ClockDomain()
+            self.clock_domains.cd_sys4x = ClockDomain()
+            self.clock_domains.cd_sys4x_ps = ClockDomain()
+            pll.create_clkout(self.cd_sys2x,    2*sys_clk_freq)
+            pll.create_clkout(self.cd_sys4x,    4*sys_clk_freq)
+            pll.create_clkout(self.cd_sys4x_ps, 4*sys_clk_freq, phase=180)
+        else:
+            self.clock_domains.cd_sys_ps = ClockDomain()
+            pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
+
+        if sdram_rate == "1:2":
+            sdram_clk = ClockSignal("sys2x_ps")
+        elif sdram_rate == "1:4":
+            sdram_clk = ClockSignal("sys4x_ps")
+        else:
+            sdram_clk = ClockSignal("sys_ps")
+
+        self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
+        pll2 = ECP5PLL()
+        self.submodules.pll2 = pll2
+        pll2.register_clkin(clk48, 48e6)
+        pll2.create_clkout(self.cd_video, 25e6)
+        pll2.create_clkout(self.cd_video5x, 125e6)
+
+        self.clock_domains.cd_usb_12 = ClockDomain()
+        self.clock_domains.cd_usb = ClockDomain()
+        self.clock_domains.cd_usb_48 = ClockDomain()
+        self.cd_usb_48 = self.cd_usb
+        pll2.create_clkout(self.cd_usb, 48e6)
+        pll2.create_clkout(self.cd_usb_12, 12e6)
+        self.comb += pll2.reset.eq(~por_done)
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+class BaseSoC(SoCCore):
+    mem_map = {**SoCCore.mem_map, **{
+        "usb_ohci":     0xc0000000,
+    }}
+    def __init__(self, revision="v0", device="12F", sdram_device="W9825G6KH6", sdram_rate="1:2", sys_clk_freq=int(40e6), toolchain="trellis", with_led_chaser=True, with_usb_host=False, with_ethernet=False, **kwargs):
+
+        platform = machdyne_konfekt.Platform(revision=revision, device=device ,toolchain=toolchain)
+
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
+
+        # SoCCore ----------------------------------------------------------------------------------
+        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Konfekt", **kwargs)
+
+        # DRAM -------------------------------------------------------------------------------------
+        if not self.integrated_main_ram_size:
+            if sdram_rate == "1:2":
+                sdrphy_cls = HalfRateGENSDRPHY
+            elif sdram_rate == "1:4":
+                sdrphy_cls = QuarterRateGENSDRPHY
+            else:
+                sdrphy_cls = GENSDRPHY
+
+            self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
+
+            if sdram_device == "W9825G6KH6":
+                self.add_sdram("sdram",
+                    phy           = self.sdrphy,
+                    module        = W9825G6KH6(sys_clk_freq, sdram_rate),
+                    l2_cache_size = kwargs.get("l2_size", 0)
+                )
+
+            if sdram_device == "IS42S16320":
+                self.add_sdram("sdram",
+                    phy           = self.sdrphy,
+                    module        = IS42S16320(self.clk_freq, sdram_rate),
+                    l2_cache_size = kwargs.get("l2_size", 0)
+                )
+
+        # USB Host ---------------------------------------------------------------------------------
+        if with_usb_host:
+            self.submodules.usb_ohci = USBOHCI(platform, platform.request("usb_host"), usb_clk_freq=int(48e6))
+            self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False))
+            self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma)
+            self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt)
+
+        # DDMI Framebuffer -------------------------------------------------------------------------------------
+        self.submodules.videophy = VideoHDMIPHY(platform.request("ddmi"),
+            clock_domain="video")
+        self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz",
+            clock_domain="video", format="rgb565")
+
+        # Leds -------------------------------------------------------------------------------------
+        if with_led_chaser:
+            self.submodules.leds = LedChaser(
+                pads         = platform.request_all("user_led"),
+                sys_clk_freq = sys_clk_freq)
+
+# Build --------------------------------------------------------------------------------------------
+
+def main():
+    from litex.soc.integration.soc import LiteXSoCArgumentParser
+    parser = LiteXSoCArgumentParser(description="LiteX SoC on Konfekt")
+    target_group = parser.add_argument_group(title="Target options")
+    target_group.add_argument("--build",           action="store_true",  help="Build design.")
+    target_group.add_argument("--load",            action="store_true",  help="Load bitstream to SRAM.")
+    target_group.add_argument("--flash",           action="store_true",  help="Flash bitstream to MMOD.")
+    target_group.add_argument("--toolchain",       default="trellis",    help="FPGA toolchain (trellis or diamond).")
+    target_group.add_argument("--sys-clk-freq",    default=40e6,         help="System clock frequency.")
+    target_group.add_argument("--revision",        default="v0",         help="Board Revision (v0).")
+    target_group.add_argument("--device",          default="12F",        help="ECP5 device (25F, 45F or 85F).")
+    target_group.add_argument("--cable",           default="usb-blaster", help="Specify an openFPGALoader cable.")
+    target_group.add_argument("--with-sdcard",     action="store_true",  help="Enable SDCard support.")
+    target_group.add_argument("--with-spi-sdcard", action="store_true",  help="Enable SPI-mode SDCard support.")
+    target_group.add_argument("--with-usb-host",   action="store_true",  help="Enable USB host support.")
+    target_group.add_argument("--boot-from-flash", action="store_true",  help="Boot from flash MMOD.")
+    target_group.add_argument("--sdram-device",    default="W9825G6KH6", help="SDRAM device (W9825G6KH6 or IS42S16320).")
+
+    builder_args(parser)
+    soc_core_args(parser)
+    trellis_args(parser)
+    args = parser.parse_args()
+
+    print("")
+    print("")
+    print("")
+    print(args)
+
+    print("")
+    print("")
+    print("")
+
+    soc = BaseSoC(
+        toolchain    = args.toolchain,
+        revision     = args.revision,
+        device       = args.device,
+        sys_clk_freq = int(float(args.sys_clk_freq)),
+        sdram_device = args.sdram_device,
+        with_usb_host = args.with_usb_host,
+        with_ethernet = args.with_ethernet,
+        **soc_core_argdict(args))
+
+    if args.with_sdcard:
+        soc.add_sdcard()
+
+    if args.with_spi_sdcard:
+        soc.add_spi_sdcard()
+
+    builder = Builder(soc, **builder_argdict(args))
+    builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
+
+    if args.build:
+        builder.build(**builder_kargs)
+
+    if args.load:
+        prog = soc.platform.create_programmer(args.cable)
+        prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
+
+    if args.flash:
+        prog = soc.platform.create_programmer(args.cable)
+        prog.flash(0x100000, builder.get_bitstream_filename(mode="sram"))
+
+if __name__ == "__main__":
+    main()

litex_boards/targets/machdyne_noir.py

@@ -0,0 +1,232 @@
+#!/usr/bin/env python3
+
+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) Greg Davill <greg.davill@gmail.com>
+# Copyright (c) Lone Dynamics Corporation <info@lonedynamics.com>
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+
+import os
+import sys
+import json
+
+from migen import *
+from litex_boards.platforms import machdyne_noir
+
+from litex.build.lattice.trellis import trellis_args, trellis_argdict
+from litex.build.io import DDROutput
+
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from litex.soc.cores.clock import *
+from litex.soc.cores.led import LedChaser
+from litex.soc.cores.usb_ohci import USBOHCI
+from litex.soc.cores.video import VideoVGAPHY
+from litex.soc.cores.video import VideoHDMIPHY
+
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.builder import *
+
+from litedram.modules import MT41K64M16, MT41K128M16, MT41K256M16, MT41K512M16
+from litedram.phy import ECP5DDRPHY
+
+from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
+from litedram.phy import QuarterRateGENSDRPHY
+
+from litex.soc.integration.soc import SoCRegion
+
+# CRG ---------------------------------------------------------------------------------------------
+
+class _CRG(Module):
+    def __init__(self, platform, sys_clk_freq, sdram_rate):
+        self.rst = Signal()
+        self.clock_domains.cd_por = ClockDomain()
+        self.clock_domains.cd_sys = ClockDomain()
+        self.clock_domains.cd_sys2x    = ClockDomain()
+        self.clock_domains.cd_sys2x_i  = ClockDomain()
+        self.clock_domains.cd_init = ClockDomain()
+        self.clock_domains.cd_video = ClockDomain()
+        self.clock_domains.cd_video5x = ClockDomain()
+
+        self.stop  = Signal()
+        self.reset = Signal()
+
+        # Clk / Rst
+        clk48 = platform.request("clk48")
+
+        # Power on reset
+        por_count = Signal(16, reset=2**16-1)
+        por_done  = Signal()
+        self.comb += self.cd_por.clk.eq(clk48)
+        self.comb += por_done.eq(por_count == 0)
+        self.sync.por += If(~por_done, por_count.eq(por_count - 1))
+
+        # PLL
+        sys2x_clk_ecsout = Signal()
+        self.submodules.pll = pll = ECP5PLL()
+        self.comb += pll.reset.eq(~por_done | self.rst)
+        pll.register_clkin(clk48, 48e6)
+        pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
+        pll.create_clkout(self.cd_init, 24e6)
+        self.specials += [
+            Instance("ECLKBRIDGECS",
+                i_CLK0   = self.cd_sys2x_i.clk,
+                i_SEL    = 0,
+                o_ECSOUT = sys2x_clk_ecsout),
+            Instance("ECLKSYNCB",
+                i_ECLKI = sys2x_clk_ecsout,
+                i_STOP  = self.stop,
+                o_ECLKO = self.cd_sys2x.clk),
+            Instance("CLKDIVF",
+                p_DIV     = "2.0",
+                i_ALIGNWD = 0,
+                i_CLKI    = self.cd_sys2x.clk,
+                i_RST     = self.reset,
+                o_CDIVX   = self.cd_sys.clk),
+            AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
+        ]
+
+        pll2 = ECP5PLL()
+        self.submodules.pll2 = pll2
+        pll2.register_clkin(clk48, 48e6)
+        pll2.create_clkout(self.cd_video, 25e6)
+        pll2.create_clkout(self.cd_video5x, 125e6)
+
+        self.clock_domains.cd_usb_12 = ClockDomain()
+        self.clock_domains.cd_usb = ClockDomain()
+        self.clock_domains.cd_usb_48 = ClockDomain()
+        self.cd_usb_48 = self.cd_usb
+        pll2.create_clkout(self.cd_usb, 48e6)
+        pll2.create_clkout(self.cd_usb_12, 12e6)
+        self.comb += pll2.reset.eq(~por_done)
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+class BaseSoC(SoCCore):
+    mem_map = {**SoCCore.mem_map, **{
+        "usb_ohci":     0xc0000000,
+    }}
+    def __init__(self, revision="v0", device="45F", sdram_device="MT41K128M16", sdram_rate="1:2", sys_clk_freq=int(40e6), toolchain="trellis", with_led_chaser=True, with_usb_host=False, with_ethernet=False, **kwargs):
+
+        platform = machdyne_noir.Platform(revision=revision, device=device ,toolchain=toolchain)
+
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
+
+        # SoCCore ----------------------------------------------------------------------------------
+        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Schoko", **kwargs)
+
+        # DDR3L ----------------------------------------------------------------------------------
+
+        if not self.integrated_main_ram_size:
+            available_sdram_modules = {
+                "MT41K64M16":  MT41K64M16,
+                "MT41K128M16": MT41K128M16,
+                "MT41K256M16": MT41K256M16,
+                "MT41K512M16": MT41K512M16,
+            }
+            sdram_module = available_sdram_modules.get(sdram_device)
+
+            ddram_pads = platform.request("ddram")
+            self.submodules.ddrphy = ECP5DDRPHY(
+                pads         = ddram_pads,
+                sys_clk_freq = sys_clk_freq,
+                cmd_delay    = 0 if sys_clk_freq > 64e6 else 100)
+            self.ddrphy.settings.rtt_nom = "disabled"
+            self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
+            self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
+            self.add_sdram("sdram",
+                phy           = self.ddrphy,
+                module        = sdram_module(sys_clk_freq, "1:2"),
+                l2_cache_size = kwargs.get("l2_size", 8192) 
+            )
+
+        # USB Host ---------------------------------------------------------------------------------
+        if with_usb_host:
+            self.submodules.usb_ohci = USBOHCI(platform, platform.request("usb_host"), usb_clk_freq=int(48e6))
+            self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False))
+            self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma)
+            self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt)
+
+        # DDMI Framebuffer -------------------------------------------------------------------------------------
+        self.submodules.videophy = VideoHDMIPHY(platform.request("ddmi"),
+            clock_domain="video")
+        self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz",
+            clock_domain="video", format="rgb565")
+
+        # Leds -------------------------------------------------------------------------------------
+        if with_led_chaser:
+            self.submodules.leds = LedChaser(
+                pads         = platform.request_all("user_led"),
+                sys_clk_freq = sys_clk_freq)
+
+# Build --------------------------------------------------------------------------------------------
+
+def main():
+    from litex.soc.integration.soc import LiteXSoCArgumentParser
+    parser = LiteXSoCArgumentParser(description="LiteX SoC on Schoko")
+    target_group = parser.add_argument_group(title="Target options")
+    target_group.add_argument("--build",           action="store_true",  help="Build design.")
+    target_group.add_argument("--load",            action="store_true",  help="Load bitstream to SRAM.")
+    target_group.add_argument("--flash",           action="store_true",  help="Flash bitstream to MMOD.")
+    target_group.add_argument("--toolchain",       default="trellis",    help="FPGA toolchain (trellis or diamond).")
+    target_group.add_argument("--sys-clk-freq",    default=40e6,         help="System clock frequency.")
+    target_group.add_argument("--revision",        default="v0",         help="Board Revision (v0).")
+    target_group.add_argument("--device",          default="45F",        help="ECP5 device (25F, 45F or 85F).")
+    target_group.add_argument("--cable",           default="usb-blaster", help="Specify an openFPGALoader cable.")
+    target_group.add_argument("--with-sdcard",     action="store_true",  help="Enable SDCard support.")
+    target_group.add_argument("--with-spi-sdcard", action="store_true",  help="Enable SPI-mode SDCard support.")
+    target_group.add_argument("--with-usb-host",   action="store_true",  help="Enable USB host support.")
+    target_group.add_argument("--with-ethernet",   action="store_true",  help="Enable ethernet support.")
+    target_group.add_argument("--boot-from-flash", action="store_true",  help="Boot from flash MMOD.")
+    target_group.add_argument("--sdram-device",    default="MT41K128M16", help="SDRAM device.")
+
+    builder_args(parser)
+    soc_core_args(parser)
+    trellis_args(parser)
+    args = parser.parse_args()
+
+    print("")
+    print("")
+    print("")
+    print(args)
+
+    print("")
+    print("")
+    print("")
+
+    soc = BaseSoC(
+        toolchain    = args.toolchain,
+        revision     = args.revision,
+        device       = args.device,
+        sys_clk_freq = int(float(args.sys_clk_freq)),
+        sdram_device = args.sdram_device,
+        with_usb_host = args.with_usb_host,
+        with_ethernet = args.with_ethernet,
+        **soc_core_argdict(args))
+
+    if args.with_sdcard:
+        soc.add_sdcard()
+
+    if args.with_spi_sdcard:
+        soc.add_spi_sdcard()
+
+    builder = Builder(soc, **builder_argdict(args))
+    builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
+
+    if args.build:
+        builder.build(**builder_kargs)
+
+    if args.load:
+        prog = soc.platform.create_programmer(args.cable)
+        prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
+
+    if args.flash:
+        prog = soc.platform.create_programmer(args.cable)
+        prog.flash(0x100000, builder.get_bitstream_filename(mode="sram"))
+
+if __name__ == "__main__":
+    main()