Add initial NewAE CW305 board support.

This commit is contained in:
Florent Kermarrec 2022-09-13 12:38:30 +02:00
parent 7b2e94b01f
commit f1899954e9
3 changed files with 143 additions and 0 deletions

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@ -175,6 +175,7 @@ Some of the suported boards, see yours? Give LiteX-Boards a try!
├── muselab_icesugar_pro
├── muselab_icesugar
├── myminieye_runber
├── newae_cw305
├── numato_aller
├── numato_mimas_a7
├── numato_nereid

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@ -0,0 +1,34 @@
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Leds
("user_led", 0, Pins("T2"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("T3"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("T4"), IOStandard("LVCMOS33")),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = []
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a100t-ftg256-2", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a100t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

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#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
# Build/Use:
# ./newae_cw305.py --csr-csr=csr.csv --build --load
# litex_server --jtag --jtag-config=openocd_xc7_ft232.cfg
# litex_term crossover
from migen import *
from litex_boards.platforms import newae_cw305
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litex.soc.cores.clock import *
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
# # #
# CFGM Clk ~65MHz.
cfgm_clk = Signal()
cfgm_clk_freq = int(65e6)
self.specials += Instance("STARTUPE2",
i_CLK = 0,
i_GSR = 0,
i_GTS = 0,
i_KEYCLEARB = 1,
i_PACK = 0,
i_USRCCLKO = cfgm_clk,
i_USRCCLKTS = 0,
i_USRDONEO = 1,
i_USRDONETS = 1,
o_CFGMCLK = cfgm_clk
)
# PLL
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(cfgm_clk, cfgm_clk_freq)
pll.create_clkout(self.cd_sys, sys_clk_freq)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
platform = newae_cw305.Platform()
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SoCCore ----------------------------------------------------------------------------------
kwargs["uart_name"] = "crossover"
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on NewAE-CW305", **kwargs)
# JTAGBone ---------------------------------------------------------------------------------
self.add_jtagbone()
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq,
)
# Build --------------------------------------------------------------------------------------------
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on NewAE-CW305")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build design.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
if args.build:
builder.build(**vivado_build_argdict(args))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if __name__ == "__main__":
main()