efinix_trion_t120_bga576: Add Tristate test code.
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@ -72,6 +72,49 @@ class BaseSoC(SoCCore):
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pads = platform.request_all("user_led"),
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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sys_clk_freq = sys_clk_freq)
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# SDRTristate Test -------------------------------------------------------------------------
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from litex.build.generic_platform import Subsignal, Pins, Misc, IOStandard
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from litex.soc.cores.bitbang import I2CMaster
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platform.add_extension([("i2c", 0,
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Subsignal("sda", Pins("T12")),
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Subsignal("scl", Pins("V11")),
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IOStandard("3.3_V_LVTTL_/_LVCMOS"),
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)])
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if True:
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self.submodules.i2c = I2CMaster(pads=platform.request("i2c"))
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if False:
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it6263 = platform.request("i2c")
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name = platform.get_pin_name(it6263.sda)
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pad = platform.get_pin_location(it6263.sda)
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sda_oe = platform.add_iface_io(name + '_OE')
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sda_i = platform.add_iface_io(name + '_IN')
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sda_o = platform.add_iface_io(name + '_OUT')
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block = {'type':'GPIO',
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'mode':'INOUT',
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'name':name,
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'location':[pad[0]],
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.delete(it6263.sda)
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name = platform.get_pin_name(it6263.scl)
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pad = platform.get_pin_location(it6263.scl)
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scl_oe = platform.add_iface_io(name + '_OE')
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scl_i = platform.add_iface_io(name + '_IN')
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scl_o = platform.add_iface_io(name + '_OUT')
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block = {'type':'GPIO',
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'mode':'INOUT',
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'name':name,
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'location':[pad[0]],
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.delete(it6263.scl)
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# Build --------------------------------------------------------------------------------------------
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# Build --------------------------------------------------------------------------------------------
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def main():
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def main():
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