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vc707: cleanup platform/targets, remove Ethernet support (no Ethernet pads defined)

This commit is contained in:
Florent Kermarrec 2020-02-25 10:35:18 +01:00
parent 3581df5af6
commit f279fe9d33
2 changed files with 94 additions and 101 deletions
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76
litex_boards/platforms/vcu118.py
View File

@ -1,10 +1,11 @@
# This file is Copyright (c) 2020 Fei Gao <feig@princeton.edu>
# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs -------------------------------------------------------------------------
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk300", 0,
@ -27,7 +28,9 @@ _io = [
Subsignal("p", Pins("H32"), IOStandard("DIFF_SSTL12")),
Subsignal("n", Pins("G32"), IOStandard("DIFF_SSTL12")),
),
("cpu_reset", 0, Pins("L19"), IOStandard("LVCMOS12")),
("user_led", 0, Pins("AT32"), IOStandard("LVCMOS12")),
("user_led", 1, Pins("AV34"), IOStandard("LVCMOS12")),
("user_led", 2, Pins("AY30"), IOStandard("LVCMOS12")),
@ -36,20 +39,24 @@ _io = [
("user_led", 5, Pins("AU37"), IOStandard("LVCMOS12")),
("user_led", 6, Pins("AV36"), IOStandard("LVCMOS12")),
("user_led", 7, Pins("BA37"), IOStandard("LVCMOS12")),
("user_dip_btn", 0, Pins("B17"), IOStandard("LVCMOS12")),
("user_dip_btn", 1, Pins("G16"), IOStandard("LVCMOS12")),
("user_dip_btn", 2, Pins("J16"), IOStandard("LVCMOS12")),
("user_dip_btn", 3, Pins("D21"), IOStandard("LVCMOS12")),
("user_btn_c", 0, Pins("BD23"), IOStandard("LVCMOS18")),
("user_btn_n", 0, Pins("BB24"), IOStandard("LVCMOS18")),
("user_btn_e", 0, Pins("BE23"), IOStandard("LVCMOS18")),
("user_btn_s", 0, Pins("BE22"), IOStandard("LVCMOS18")),
("user_btn_w", 0, Pins("BF22"), IOStandard("LVCMOS18")),
("i2c", 0,
Subsignal("scl", Pins("AM24"), IOStandard("LVCMOS18")),
Subsignal("sda", Pins("AL24"), IOStandard("LVCMOS18")),
),
("i2c_mux_reset_n", 0, Pins("AL25"), IOStandard("LVCMOS18")),
("serial", 0,
Subsignal("rx", Pins("AW25"), IOStandard("LVCMOS18")),
Subsignal("rts", Pins("BB22"), IOStandard("LVCMOS18")),
@ -59,7 +66,10 @@ _io = [
# DDR4 memory channel C1. Only use the first 64 data bits
("ddram", 0,
Subsignal("a", Pins("D14 B15 B16 C14 C15 A13 A14 A15 A16 B12 C12 B13 C13 D15"), IOStandard("SSTL12")),
Subsignal("a", Pins(
"D14 B15 B16 C14 C15 A13 A14 A15",
"A16 B12 C12 B13 C13 D15"),
IOStandard("SSTL12")),
Subsignal("ba", Pins("G15 G13"), IOStandard("SSTL12")),
Subsignal("bg", Pins("H13"), IOStandard("SSTL12")),
Subsignal("ras_n", Pins("F15"), IOStandard("SSTL12")),
@ -70,8 +80,19 @@ _io = [
Subsignal("ten", Pins("A20"), IOStandard("POD12")),
Subsignal("alert_n", Pins("R17"), IOStandard("POD12")),
Subsignal("par", Pins("G10"), IOStandard("POD12")),
Subsignal("dm", Pins("G11 R18 K17 G18 B18 P20 L23 G22"), IOStandard("POD12")),
Subsignal("dq", Pins("F11 E11 F10 F9 H12 G12 E9 D9 R19 P19 M18 M17 N19 N18 N17 M16 L16 K16 L18 K18 J17 H17 H19 H18 F19 F18 E19 E18 G20 F20 E17 D16 D17 C17 C19 C18 D20 D19 C20 B20 N23 M23 R21 P21 R22 P22 T23 R23 K24 J24 M21 L21 K21 J21 K22 J22 H23 H22 E23 E22 F21 E21 F24 F23"), IOStandard("POD12")),
Subsignal("dm", Pins(
"G11 R18 K17 G18 B18 P20 L23 G22"),
IOStandard("POD12")),
Subsignal("dq", Pins(
"F11 E11 F10 F9 H12 G12 E9 D9",
"R19 P19 M18 M17 N19 N18 N17 M16",
"L16 K16 L18 K18 J17 H17 H19 H18",
"F19 F18 E19 E18 G20 F20 E17 D16",
"D17 C17 C19 C18 D20 D19 C20 B20",
"N23 M23 R21 P21 R22 P22 T23 R23",
"K24 J24 M21 L21 K21 J21 K22 J22",
"H23 H22 E23 E22 F21 E21 F24 F23"),
IOStandard("POD12")),
Subsignal("dqs_p", Pins("D11 P17 K19 F16 A19 N22 M20 H24"), IOStandard("DIFF_POD12")),
Subsignal("dqs_n", Pins("D10 P16 J19 E16 A18 M22 L20 G23"), IOStandard("DIFF_POD12")),
Subsignal("clk_p", Pins("F14"), IOStandard("DIFF_POD12")),
@ -83,7 +104,10 @@ _io = [
# DDR4 memory channel C2.
("ddram_second_channel", 0,
Subsignal("a", Pins("AM27 AL27 AP26 AP25 AN28 AM28 AP28 AP27 AN26 AM26 AR28 AR27 AV25 AT25"), IOStandard("SSTL12")),
Subsignal("a", Pins(
"AM27 AL27 AP26 AP25 AN28 AM28 AP28 AP27",
"AN26 AM26 AR28 AR27 AV25 AT25"),
IOStandard("SSTL12")),
Subsignal("ba", Pins("AR25 AU28"), IOStandard("SSTL12")),
Subsignal("bg", Pins("AU27"), IOStandard("SSTL12")),
Subsignal("ras_n", Pins("AV26"), IOStandard("SSTL12")),
@ -94,10 +118,27 @@ _io = [
Subsignal("ten", Pins("AY35"), IOStandard("POD12")),
Subsignal("alert_n", Pins("AR29"), IOStandard("SSTL12")),
Subsignal("par", Pins("BF29"), IOStandard("POD12")),
Subsignal("dm", Pins("BE32 BB31 AV33 AR32 BC34 BE40 AY37 AV35 BE29 BA29"), IOStandard("SSTL12")),
Subsignal("dq", Pins("BD30 BE30 BD32 BE33 BC33 BD33 BC31 BD31 BA32 BB33 BA30 BA31 AW31 AW32 AY32 AY33 AV30 AW30 AU33 AU34 AT31 AU32 AU31 AV31 AR33 AT34 AT29 AT30 AP30 AR30 AN30 AN31 BE34 BF34 BC35 BC36 BD36 BE37 BF36 BF37 BD37 BE38 BC39 BD40 BB38 BB39 BC38 BD38 BB36 BB37 BA39 BA40 AW40 AY40 AY38 AY39 AW35 AW36 AU40 AV40 AU38 AU39 AV38 AV39 BF26 BF27 BD28 BE28 BD27 BE27 BD25 BD26 BC25 BC26 BB28 BC28 AY27 AY28 BA27 BB27"), IOStandard("POD12")),
Subsignal("dqs_p", Pins("BF30 AY34 AU29 AP31 BE35 BE39 BA35 AW37 BE25 BA26"), IOStandard("DIFF_POD12")),
Subsignal("dqs_n", Pins("BF31 BA34 AV29 AP32 BF35 BF39 BA36 AW38 BF25 BB26"), IOStandard("DIFF_POD12")),
Subsignal("dm", Pins(
"BE32 BB31 AV33 AR32 BC34 BE40 AY37 AV35 BE29 BA29"),
IOStandard("SSTL12")),
Subsignal("dq", Pins(
"BD30 BE30 BD32 BE33 BC33 BD33 BC31 BD31",
"BA32 BB33 BA30 BA31 AW31 AW32 AY32 AY33",
"AV30 AW30 AU33 AU34 AT31 AU32 AU31 AV31",
"AR33 AT34 AT29 AT30 AP30 AR30 AN30 AN31",
"BE34 BF34 BC35 BC36 BD36 BE37 BF36 BF37",
"BD37 BE38 BC39 BD40 BB38 BB39 BC38 BD38",
"BB36 BB37 BA39 BA40 AW40 AY40 AY38 AY39",
"AW35 AW36 AU40 AV40 AU38 AU39 AV38 AV39",
"BF26 BF27 BD28 BE28 BD27 BE27 BD25 BD26",
"BC25 BC26 BB28 BC28 AY27 AY28 BA27 BB27"),
IOStandard("POD12")),
Subsignal("dqs_p", Pins(
"BF30 AY34 AU29 AP31 BE35 BE39 BA35 AW37 BE25 BA26"),
IOStandard("DIFF_POD12")),
Subsignal("dqs_n", Pins(
"BF31 BA34 AV29 AP32 BF35 BF39 BA36 AW38 BF25 BB26"),
IOStandard("DIFF_POD12")),
Subsignal("clk_p", Pins("AT26"), IOStandard("DIFF_POD12")),
Subsignal("clk_n", Pins("AT27"), IOStandard("DIFF_POD12")),
Subsignal("cke", Pins("AW28"), IOStandard("SSTL12")),
@ -106,25 +147,18 @@ _io = [
),
]
# Connectors ------------------------------------------------------------------
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
]
_connectors = []
# Platform --------------------------------------------------------------------
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_period = 1e9 / 125e6
default_clk_period = 1e9/125e6
def __init__(self):
XilinxPlatform.__init__(
self,
"xcvu9p-flga2104-2-e",
_io,
_connectors,
toolchain="vivado"
)
XilinxPlatform.__init__(self, "xcvu9p-flga2104-2-e", _io, _connectors, toolchain="vivado")
def create_programmer(self):
return VivadoProgrammer()

59
litex_boards/targets/vcu118.py
View File

@ -1,23 +1,21 @@
#!/usr/bin/env python3
# This file is Copyright (c) 2020 Fei Gao <feig@princeton.edu>
# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
import argparse
from migen import *
from litex.boards.platforms import vcu118
from litex_boards.platforms import vcu118
from litex.soc.cores.clock import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import EDY4016A
from litedram.phy import uspddrphy
from liteeth.phy.ku_1000basex import KU_1000BASEX
from liteeth.mac import LiteEthMAC
from litedram.phy import usddrphy
# CRG ----------------------------------------------------------------------------------------------
@ -88,65 +86,26 @@ class BaseSoC(SoCSDRAM):
# DDR4 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = uspddrphy.USPDDRPHY(platform.request("ddram"),
self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
memtype = "DDR4",
sys_clk_freq = sys_clk_freq)
sys_clk_freq = sys_clk_freq,
sim_device = "ULTRASCALE_PLUS")
self.add_csr("ddrphy")
self.add_constant("USPDDRPHY", None)
self.add_constant("USDDRPHY", None)
sdram_module = EDY4016A(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings = sdram_module.geom_settings,
timing_settings = sdram_module.timing_settings)
# EthernetSoC --------------------------------------------------------------------------------------
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
# Ethernet ---------------------------------------------------------------------------------
# phy
self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk,
data_pads = self.platform.request("sfp", 0),
sys_clk_freq = self.clk_freq)
self.add_csr("ethphy")
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
# mac
self.submodules.ethmac = LiteEthMAC(
phy = self.ethphy,
dw = 32,
interface = "wishbone",
endianness = self.cpu.endianness)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints
self.platform.add_period_constraint(self.ethphy.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.cd_eth_rx.clk,
self.ethphy.cd_eth_tx.clk)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on KCU105")
parser = argparse.ArgumentParser(description="LiteX SoC on VCU118")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
args = parser.parse_args()
cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(**soc_sdram_argdict(args))
soc = BaseSoC(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()