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zybo_z7: fix clock pin constraint 

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi 2020-12-07 16:46:20 +01:00
parent 26d3b57243
commit f66860c201
1 changed files with 1 additions and 1 deletions
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2
litex_boards/platforms/zybo_z7.py
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@ -11,7 +11,7 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
_io = [ _io = [
# Clk / Rst # Clk / Rst
("clk125", 0, Pins("L16"), IOStandard("LVCMOS33")), ("clk125", 0, Pins("K17"), IOStandard("LVCMOS33")),
# Leds # Leds
("user_led", 0, Pins("M14"), IOStandard("LVCMOS33")), ("user_led", 0, Pins("M14"), IOStandard("LVCMOS33")),