zybo_z7: fix clock pin constraint

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-12-07 16:46:20 +01:00 · 2020-12-07 16:46:20 +01:00 · f66860c201
parent 26d3b57243
commit f66860c201
1 changed files with 1 additions and 1 deletions
--- a/litex_boards/platforms/zybo_z7.py
+++ b/litex_boards/platforms/zybo_z7.py
@ -11,7 +11,7 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer

 _io = [
    # Clk / Rst
-    ("clk125", 0, Pins("L16"), IOStandard("LVCMOS33")),
+    ("clk125", 0, Pins("K17"), IOStandard("LVCMOS33")),

    # Leds
    ("user_led", 0, Pins("M14"), IOStandard("LVCMOS33")),