Fix orangecrab target
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@ -69,7 +69,7 @@ class _CRG(Module):
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reset_timer = WaitTimer(sys_clk_freq)
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self.submodules += reset_timer
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self.comb += reset_timer.wait.eq(~rst_n)
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self.comb += platform.request("rst_n").eq(reset_timer.done)
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self.comb += platform.request("rst_n").eq(~reset_timer.done)
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class _CRGSDRAM(Module):
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