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terasic_deca: Remove enforced CPU variant/debug: --cpu-variant=imac or --cpu-variant=imac+debug can be used for this. 

The default CPU/Variant is defined in LiteX, enforcing the variant on the target
prevent usage of the other CPUs and also complicate maintenance.
This commit is contained in:
Florent Kermarrec 2021-03-27 08:56:46 +01:00
parent 4daf78c5c7
commit f714e1210a
1 changed files with 0 additions and 3 deletions
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3
litex_boards/targets/terasic_deca.py
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@ -84,7 +84,6 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DECA") parser = argparse.ArgumentParser(description="LiteX SoC on DECA")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--debug", action="store_true", help="generate cpu debug interface") # FIXME: Remove or add argument in LiteX directly.
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)") parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)")
parser.add_argument("--integrated-ram-size", default=0x4000, help="Use FPGA block RAM as main RAM. Interim measure until we have DDR3 support.") parser.add_argument("--integrated-ram-size", default=0x4000, help="Use FPGA block RAM as main RAM. Interim measure until we have DDR3 support.")
@ -96,8 +95,6 @@ def main():
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq = int(float(args.sys_clk_freq)),
with_video_terminal = args.with_video_terminal, with_video_terminal = args.with_video_terminal,
integrated_main_ram_size = args.integrated_ram_size, integrated_main_ram_size = args.integrated_ram_size,
# Use compressed instructions to save ROM
cpu_variant = "imac+debug" if args.debug else "imac", # FIXME: Remove or add argument in LiteX directly.
**soc_core_argdict(args) **soc_core_argdict(args)
) )
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))