Adding target to files
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Goran Mahovlic
GitHub
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2021 Greg Davill <greg.davill@gmail.com>
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# Copyright (c) 2022 Goran Mahovlic <goran.mahovlic@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# Build/Use:
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# ./gsd_ulx4m_ld.py --uart-name=uart --uart-baudrate=115200 --sdram-device MT41K64M16 --csr-csv=csr.csv --build
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import os
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import sys
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import ulx4m_ld_v2
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.gpio import GPIOTristate
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from litex.soc.cores.video import VideoHDMIPHY
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from litedram.common import PHYPadsReducer
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from litedram.modules import MT41K64M16,MT41K128M16,MT41K256M16,MT41K512M16
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from litedram.phy import ECP5DDRPHY
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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# CRG ---------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_video_pll=True):
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self.rst = Signal()
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self.clock_domains.cd_init = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
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# # #
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self.stop = Signal()
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self.reset = Signal()
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# Clk / Rst
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clk25 = platform.request("clk25")
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rst_n = platform.request("rst_n", 0)
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk25)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# USB PLL
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# if with_usb_pll:
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# self.submodules.usb_pll = usb_pll = ECP5PLL()
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# self.comb += usb_pll.reset.eq(rst | self.rst)
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# usb_pll.register_clkin(clk25, 25e6)
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# self.clock_domains.cd_usb_12 = ClockDomain()
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# self.clock_domains.cd_usb_48 = ClockDomain()
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# usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0)
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# usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0)
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# Video PLL
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if with_video_pll:
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self.submodules.video_pll = video_pll = ECP5PLL()
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self.comb += video_pll.reset.eq(rst_n | self.rst)
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video_pll.register_clkin(clk25, 25e6)
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self.clock_domains.cd_hdmi = ClockDomain()
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self.clock_domains.cd_hdmi5x = ClockDomain()
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video_pll.create_clkout(self.cd_hdmi, 25e6, margin=0)
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video_pll.create_clkout(self.cd_hdmi5x, 125e6, margin=0)
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# PLL
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | rst_n | self.rst)
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pll.register_clkin(clk25, 25e6)
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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pll.create_clkout(self.cd_init, 25e6)
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self.specials += [
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Instance("ECLKSYNCB",
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i_ECLKI = self.cd_sys2x_i.clk,
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i_STOP = self.stop,
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o_ECLKO = self.cd_sys2x.clk),
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Instance("CLKDIVF",
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p_DIV = "1.0",
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i_ALIGNWD = 0,
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i_CLKI = self.cd_sys2x.clk,
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i_RST = self.reset,
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o_CDIVX = self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
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AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset),
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]
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# BaseSoC ------------------------------------------------------------------------------------------
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# revision = kwargs.get("revision", "0.1")
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# device = kwargs.get("device", "UM-45F")
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class BaseSoC(SoCCore):
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def __init__(self, revision="0.1", device="UM5G-85F", sdram_device="MT41K512M16", sys_clk_freq=int(100e6),
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toolchain="trellis", with_ethernet=False, with_etherbone=False,
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with_video_terminal=True,
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with_video_framebuffer=False,
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eth_ip="192.168.1.50",
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eth_dynamic_ip = False,
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with_spi_flash = False,
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with_led_chaser = True,
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with_syzygy_gpio = False,
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**kwargs) :
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platform = ulx4m_ld_v2.Platform(revision="0.1", device="UM5G-85F" ,toolchain="trellis")
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# SoCCore ----------------------------------------------------------------------------------
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if kwargs["uart_name"] in ["serial", "usb_acm"]:
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kwargs["uart_name"] = "serial"
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on ULX4M-LD-V2",
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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with_video_pll = with_video_terminal or with_video_framebuffer
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self.submodules.crg = _CRG(platform, sys_clk_freq, with_video_pll)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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available_sdram_modules = {
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"MT41K64M16": MT41K64M16,
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"MT41K128M16": MT41K128M16,
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"MT41K256M16": MT41K256M16,
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"MT41K512M16": MT41K256M16,
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}
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sdram_module = available_sdram_modules.get(sdram_device)
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self.submodules.ddrphy = ECP5DDRPHY(
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pads = PHYPadsReducer(platform.request("ddram"), [0, 1]),
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sys_clk_freq=sys_clk_freq)
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self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
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self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = sdram_module(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import IS25LP128
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x", module=IS25LP128(Codes.READ_1_1_4))
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal or with_video_framebuffer:
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self.submodules.videophy = VideoHDMIPHY(platform.request("gpdi"), clock_domain="hdmi")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# GPIOs ------------------------------------------------------------------------------------
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if with_syzygy_gpio:
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platform.add_extension(ulx4m_ld_v2.raw_syzygy_io("SYZYGY0"))
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self.submodules.gpio = GPIOTristate(platform.request("SYZYGY0"))
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on ULX4M-LD-V2")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
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parser.add_argument("--revision", default="1.0", help="Board Revision (1.0).")
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parser.add_argument("--device", default="UM5G-85F", help="ECP5 device (25F, 45F, 85F).")
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parser.add_argument("--sdram-device", default="MT41K32M16", help="SDRAM device (MT41K64M16, MT41K128M16, MT41K256M16 or MT41K512M16).")
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ethopts = parser.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Add Ethernet.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Add EtherBone.")
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parser.add_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
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parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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sdopts = parser.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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parser.add_argument("--with-syzygy-gpio",action="store_true", help="Enable GPIOs through SYZYGY Breakout on Port-A.")
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viopts = parser.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
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builder_args(parser)
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soc_core_args(parser)
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trellis_args(parser)
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args = parser.parse_args()
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assert not (args.with_etherbone and args.eth_dynamic_ip)
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soc = BaseSoC(
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toolchain = args.toolchain,
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revision = args.revision,
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device = args.device,
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sdram_device = args.sdram_device,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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with_spi_flash = args.with_spi_flash,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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with_syzygy_gpio = args.with_syzygy_gpio,
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**soc_core_argdict(args))
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
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builder.build(**builder_kargs, run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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