Merge pull request #117 from YanekJ/mist_board
Initial support for the MIST board (https://github.com/mist-devel/mis…
This commit is contained in:
enjoy-digital
GitHub
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f83cd04c43
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#
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# This file is part of LiteX-Boards.
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#
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.altera import AlteraPlatform
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from litex.build.altera.programmer import USBBlaster
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk27", 0, Pins("54")),
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("clk27", 0, Pins("54")),
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("user_led", 0, Pins("7"),
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Misc("CURRENT_STRENGTH_NEW 4MA")),
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("vga", 0,
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Subsignal("r", Pins("135 137 141 142 143 144")),
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Subsignal("g", Pins("106 110 111 112 113 114")),
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Subsignal("b", Pins("115 120 121 125 132 133")),
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Subsignal("vsync", Pins("136")),
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Subsignal("hsync", Pins("119")),
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Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""),
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),
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("audio", 0,
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Subsignal("l", Pins("65")),
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Subsignal("r", Pins("80")),
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Misc("CURRENT_STRENGTH_NEW 4MA"),
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),
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("serial", 0,
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Subsignal("tx", Pins("46")),
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Subsignal("rx", Pins("31")),
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),
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("spi", 0,
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Subsignal("do", Pins("105")),
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Subsignal("di", Pins("88")),
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Subsignal("sck", Pins("126")),
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Subsignal("ss2", Pins("127")),
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Subsignal("ss3", Pins("91")),
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Subsignal("ss4", Pins("90")),
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),
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("conf_data0", 0, Pins("13")),
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("sdram_clock", 0, Pins("43"),
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Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("a", Pins("49 44 42 39 4 6 8 10 11 28 50 30 32")),
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Subsignal("dq", Pins("83 79 77 76 72 71 69 68 86 87 98 99 100 101 103 104"),
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Misc("FAST_INPUT_REGISTER ON"), Misc("FAST_OUTPUT_ENABLE_REGISTER ON")),
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Subsignal("ba", Pins("58 51")),
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Subsignal("dm", Pins("67 85")), # DQML, DQMH
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Subsignal("ras_n", Pins("60")),
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Subsignal("cas_n", Pins("64")),
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Subsignal("we_n", Pins("66")),
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Subsignal("cs_n", Pins("59")),
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Subsignal("cke", Pins("33")),
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Misc("FAST_OUTPUT_REGISTER ON"),
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Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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default_clk_name = "clk27"
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default_clk_period = 1e9/27e6
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def __init__(self):
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AlteraPlatform.__init__(self, "EP3C25E144C8", _io)
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self.add_platform_command("set_global_assignment -name FAMILY \"Cyclone III\"")
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self.add_platform_command("set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144")
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self.add_platform_command("set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED")
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self.add_platform_command("set_global_assignment -name USE_CONFIGURATION_DEVICE OFF")
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self.add_platform_command("set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME \"PASSIVE SERIAL\"")
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self.add_platform_command("set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP \"AS INPUT TRI-STATED\"")
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self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
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self.add_platform_command("set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
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self.add_platform_command("set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
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self.add_platform_command("set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
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self.add_platform_command("set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
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self.add_platform_command("set_global_assignment -name STRATIX_DEVICE_IO_STANDARD \"3.3-V LVTTL\"")
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def create_programmer(self):
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return USBBlaster()
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def do_finalize(self, fragment):
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AlteraPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk27", 0, loose=True), 1e9/27e6)
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self.add_period_constraint(self.lookup_request("clk27", 1, loose=True), 1e9/27e6)
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@ -0,0 +1,121 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import DDROutput
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from litex_boards.platforms import mist
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from litex.soc.cores.clock import CycloneIVPLL
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT48LC16M16
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from litedram.phy import GENSDRPHY
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from litevideo.terminal.core import Terminal
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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self.clock_domains.cd_vga = ClockDomain(reset_less=True)
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# # #
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# Clk / Rst
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clk27 = platform.request("clk27")
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# PLL
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self.submodules.pll = pll = CycloneIVPLL(speedgrade="-8")
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pll.register_clkin(clk27, 27e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_vga, 25e6)
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# SDRAM clock
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), with_vga=False, **kwargs):
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platform = mist.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on MIST",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = MT48LC16M16(sys_clk_freq, "1:1"),
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origin = self.mem_map["main_ram"],
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size = kwargs.get("max_sdram_size", 0x2000000),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
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l2_cache_reverse = True
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)
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# VGA Terminal -----------------------------------------------------------------------------
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if with_vga:
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self.submodules.terminal = terminal = Terminal()
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self.bus.add_slave("terminal", self.terminal.bus, region=SoCRegion(origin=0x30000000, size=0x10000))
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vga_pads = platform.request("vga")
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self.comb += [
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vga_pads.vsync.eq(terminal.vsync),
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vga_pads.hsync.eq(terminal.hsync),
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vga_pads.r.eq(terminal.red[2:8]),
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vga_pads.g.eq(terminal.green[2:8]),
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vga_pads.b.eq(terminal.blue[2:8])
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]
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on MIST")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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builder_args(parser)
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soc_sdram_args(parser)
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parser.add_argument("--with-vga", action="store_true", help="Enable VGA support")
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args = parser.parse_args()
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soc = BaseSoC(with_vga=args.with_vga, **soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
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if __name__ == "__main__":
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main()
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@ -72,6 +72,9 @@ class TestTargets(unittest.TestCase):
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# Xilinx Virtex Ultrascale+
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platforms.append("vcu118")
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# Intel Cyclone3
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platforms.append("mist")
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# Intel Cyclone4
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platforms.append("de0nano")
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platforms.append("de2_115")
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