targets/kc705: simplify SATA using LiteX's add_sata integration method.
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@ -89,11 +89,7 @@ class BaseSoC(SoCCore):
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# SATA (Experimental) ----------------------------------------------------------------------
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# SATA (Experimental) ----------------------------------------------------------------------
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if with_sata:
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if with_sata:
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from litex.build.generic_platform import Subsignal, Pins
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from litex.build.generic_platform import Subsignal, Pins
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from litex.soc.interconnect import wishbone
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from litesata.phy import LiteSATAPHY
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from litesata.phy import LiteSATAPHY
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from litesata.core import LiteSATACore
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from litesata.frontend.arbitration import LiteSATACrossbar
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from litesata.frontend.dma import LiteSATABlock2MemDMA
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# IOs
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# IOs
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_sata_io = [
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_sata_io = [
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@ -120,29 +116,10 @@ class BaseSoC(SoCCore):
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gen = "gen2",
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gen = "gen2",
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clk_freq = sys_clk_freq,
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clk_freq = sys_clk_freq,
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data_width = 16)
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data_width = 16)
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self.add_csr("sata_phy")
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# Core
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# Core
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self.submodules.sata_core = LiteSATACore(self.sata_phy)
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self.add_sata(phy=self.sata_phy, mode="read")
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# Crossbar
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self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
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# Block2Mem DMA
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bus = wishbone.Interface(data_width=32, adr_width=32)
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self.submodules.sata_block2mem = LiteSATABlock2MemDMA(
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user_port = self.sata_crossbar.get_port(),
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bus = bus,
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endianness = self.cpu.endianness)
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self.bus.add_master("sata_block2mem", master=bus)
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self.add_csr("sata_block2mem")
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# Timing constraints
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platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/150e6)
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platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/150e6)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.sata_phy.crg.cd_sata_tx.clk,
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self.sata_phy.crg.cd_sata_tx.clk)
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# Leds -------------------------------------------------------------------------------------
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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self.submodules.leds = LedChaser(
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