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platforms: ddr4 datacenter: invert eth clocks 

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi 2021-11-16 12:55:33 +01:00
parent 45f9e25b5a
commit fa26b126df
1 changed files with 2 additions and 2 deletions
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4
litex_boards/platforms/antmicro_datacenter_ddr4_test_board.py
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@ -82,8 +82,8 @@ _io = [
# RGMII Ethernet # RGMII Ethernet
("eth_ref_clk", 0, Pins("AA23"), IOStandard("LVCMOS33")), ("eth_ref_clk", 0, Pins("AA23"), IOStandard("LVCMOS33")),
("eth_clocks", 0, ("eth_clocks", 0,
Subsignal("tx", Pins("Y23")), Subsignal("rx", Pins("Y23")),
Subsignal("rx", Pins("AA24")), Subsignal("tx", Pins("AA24")),
IOStandard("LVCMOS33") IOStandard("LVCMOS33")
), ),
("eth", 0, ("eth", 0,