DECA: Add Ethernet and Etherbone support
Also fixed pcf_en IO standard compared to golden Arrow project.
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597e5ca142
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fbd424fc48
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@ -191,7 +191,7 @@ _io = [
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Subsignal("tx_data", Pins("U2 W1 N9 W2")),
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Subsignal("tx_data", Pins("U2 W1 N9 W2")),
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Subsignal("col", Pins("R4")),
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Subsignal("col", Pins("R4")),
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Subsignal("crs", Pins("P5")),
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Subsignal("crs", Pins("P5")),
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Subsignal("pcf_en", Pins("V9"), IOStandard("3.3 V")),
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Subsignal("pcf_en", Pins("V9"), IOStandard("3.3-V LVTTL")),
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IOStandard("2.5 V"),
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IOStandard("2.5 V"),
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),
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),
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@ -306,3 +306,6 @@ class Platform(AlteraPlatform):
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def do_finalize(self, fragment):
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def do_finalize(self, fragment):
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AlteraPlatform.do_finalize(self, fragment)
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AlteraPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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# Generate PLL clocsk in STA
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self.toolchain.additional_sdc_commands.append("derive_pll_clocks -create_base_clocks -use_net_name")
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self.toolchain.additional_sdc_commands.append("derive_clock_uncertainty")
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@ -17,7 +17,8 @@ from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoDVIPHY
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from litex.soc.cores.video import VideoDVIPHY
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.bitbang import I2CMaster
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from liteeth.phy.mii import LiteEthPHYMII
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# CRG ----------------------------------------------------------------------------------------------
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# CRG ----------------------------------------------------------------------------------------------
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@ -53,6 +54,8 @@ class _CRG(Module):
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class BaseSoC(SoCCore):
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_video_terminal=False,
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def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_video_terminal=False,
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with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50",
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eth_dynamic_ip=False,
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**kwargs):
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**kwargs):
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self.platform = platform = deca.Platform()
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self.platform = platform = deca.Platform()
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@ -68,6 +71,23 @@ class BaseSoC(SoCCore):
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# CRG --------------------------------------------------------------------------------------
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = self.crg = _CRG(platform, sys_clk_freq, with_usb_pll=False)
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self.submodules.crg = self.crg = _CRG(platform, sys_clk_freq, with_usb_pll=False)
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# Ethernet ---------------------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.platform.toolchain.additional_sdc_commands += [
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'create_clock -name eth_rx_clk -period 40.0 [get_ports {eth_clocks_rx}]',
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'create_clock -name eth_tx_clk -period 40.0 [get_ports {eth_clocks_tx}]',
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'set_false_path -from [get_clocks {sys_clk}] -to [get_clocks {eth_rx_clk}]',
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'set_false_path -from [get_clocks {sys_clk}] -to [get_clocks {eth_tx_clk}]',
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'set_false_path -from [get_clocks {eth_rx_clk}] -to [get_clocks {eth_tx_clk}]',
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]
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self.submodules.ethphy = LiteEthPHYMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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# Video ------------------------------------------------------------------------------------
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal:
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if with_video_terminal:
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self.submodules.videophy = VideoDVIPHY(platform.request("hdmi"), clock_domain="hdmi")
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self.submodules.videophy = VideoDVIPHY(platform.request("hdmi"), clock_domain="hdmi")
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@ -86,6 +106,11 @@ def main():
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
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parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
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ethopts = parser.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
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parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
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parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
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builder_args(parser)
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builder_args(parser)
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soc_core_args(parser)
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soc_core_args(parser)
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@ -93,6 +118,10 @@ def main():
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soc = BaseSoC(
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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with_video_terminal = args.with_video_terminal,
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with_video_terminal = args.with_video_terminal,
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**soc_core_argdict(args)
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**soc_core_argdict(args)
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)
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)
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