Merge pull request #473 from antmicro/crosslink-nx-zephyr
Add support for SDI-MIPI Video Converter
This commit is contained in:
enjoy-digital
GitHub
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fe2be83feb
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import LatticeProgrammer
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from litex.build.lattice.programmer import EcpprogProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk12", 0, Pins("G15"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("J12"), IOStandard("LVCMOS33")),
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Subsignal("rx", Pins("J11"), IOStandard("LVCMOS33")),
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),
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# Section 7.3 General Purpose LEDs
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("user_led", 0, Pins("E15"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("E16"), IOStandard("LVCMOS33")),
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# Section 7.1 DIP Switch
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("user_dip_btn", 0, Pins("F15"), IOStandard("LVCMOS33")),
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("user_dip_btn", 1, Pins("H10"), IOStandard("LVCMOS33")),
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# Section 6.3.1. SPI Configuration
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("spiflash", 0,
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Subsignal("cs_n", Pins("C15")),
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Subsignal("clk", Pins("C16")),
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Subsignal("mosi", Pins("C14")),
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Subsignal("miso", Pins("D16")),
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IOStandard("LVCMOS33")
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)
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = []
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# Test and Demo ------------------------------------------------------------------------------------
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk12"
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default_clk_period = 1e9/12e6
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def __init__(self, device="LIFCL-40-9BG400C", toolchain="radiant", **kwargs):
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# Accept "LIFCL" for backwards compatibility.
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# LIFCL just means Crosslink-NX so we can expect every
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# Crosslink-NX Evaluation Board to have a LIFCL part.
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if device == "LIFCL":
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device == "LIFCL-40-9BG400C"
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assert device in ["LIFCL-40-9BG256C", "LIFCL-40-9BG400C", "LIFCL-40-8BG400CES", "LIFCL-40-8BG400CES2", "LIFCL-40-8BG400C"]
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LatticePlatform.__init__(self, device, _io, _connectors, toolchain=toolchain, **kwargs)
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def create_programmer(self, mode="direct", prog="radiant"):
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assert mode in ["direct", "flash"]
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assert prog in ["radiant", "ecpprog"]
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if prog == "ecpprog":
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return EcpprogProgrammer()
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xcf_template_direct = """<?xml version='1.0' encoding='utf-8' ?>
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<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
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<ispXCF version="R1.2.0">
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<Comment></Comment>
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<Chain>
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<Comm>JTAG</Comm>
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<Device>
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<SelectedProg value="TRUE"/>
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<Pos>1</Pos>
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<Vendor>Lattice</Vendor>
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<Family>LIFCL</Family>
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<Name>LIFCL-40</Name>
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<IDCode>0x010f1043</IDCode>
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<Package>All</Package>
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<PON>LIFCL-40</PON>
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<Bypass>
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<InstrLen>8</InstrLen>
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<InstrVal>11111111</InstrVal>
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<BScanLen>1</BScanLen>
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<BScanVal>0</BScanVal>
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</Bypass>
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<File>{bitstream_file}</File>
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<JedecChecksum>N/A</JedecChecksum>
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<MemoryType>Static Random Access Memory (SRAM)</MemoryType>
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<Operation>Fast Configuration</Operation>
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<Option>
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<SVFVendor>JTAG STANDARD</SVFVendor>
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<IOState>HighZ</IOState>
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<PreloadLength>362</PreloadLength>
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<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
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<Usercode>0x00000000</Usercode>
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<AccessMode>Direct Programming</AccessMode>
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</Option>
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</Device>
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</Chain>
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<ProjectOptions>
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<Program>SEQUENTIAL</Program>
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<Process>ENTIRED CHAIN</Process>
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<OperationOverride>No Override</OperationOverride>
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<StartTAP>TLR</StartTAP>
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<EndTAP>TLR</EndTAP>
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<VerifyUsercode value="FALSE"/>
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<TCKDelay>3</TCKDelay>
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</ProjectOptions>
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<CableOptions>
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<CableName>USB2</CableName>
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<PortAdd>FTUSB-0</PortAdd>
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</CableOptions>
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</ispXCF>
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"""
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xcf_template_flash = """<?xml version='1.0' encoding='utf-8' ?>
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<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
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<ispXCF version="R1.2.0">
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<Comment></Comment>
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<Chain>
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<Comm>JTAG2SPI</Comm>
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<Device>
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<SelectedProg value="TRUE"/>
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<Pos>1</Pos>
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<Vendor>Lattice</Vendor>
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<Family>LIFCL</Family>
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<Name>LIFCL-40</Name>
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<Package>All</Package>
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<Bypass>
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<InstrLen>8</InstrLen>
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<InstrVal>11111111</InstrVal>
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<BScanLen>1</BScanLen>
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<BScanVal>0</BScanVal>
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</Bypass>
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<File>{bitstream_file}</File>
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<MemoryType>External SPI Flash Memory (SPI FLASH)</MemoryType>
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<Operation>Erase,Program,Verify</Operation>
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<Option>
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<SVFVendor>JTAG STANDARD</SVFVendor>
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<Usercode>0x00000000</Usercode>
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<AccessMode>Direct Programming</AccessMode>
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</Option>
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<FPGALoader>
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<CPLDDevice>
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<Device>
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<Pos>1</Pos>
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<Vendor>Lattice</Vendor>
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<Family>LIFCL</Family>
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<Name>LIFCL-40</Name>
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<IDCode>0x010f1043</IDCode>
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<Package>All</Package>
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<PON>LIFCL-40</PON>
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<Bypass>
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<InstrLen>8</InstrLen>
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<InstrVal>11111111</InstrVal>
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<BScanLen>1</BScanLen>
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<BScanVal>0</BScanVal>
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</Bypass>
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<MemoryType>Static Random Access Memory (SRAM)</MemoryType>
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<Operation>Refresh Verify ID</Operation>
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<Option>
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<SVFVendor>JTAG STANDARD</SVFVendor>
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<IOState>HighZ</IOState>
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<PreloadLength>362</PreloadLength>
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<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
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<AccessMode>Direct Programming</AccessMode>
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</Option>
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</Device>
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</CPLDDevice>
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<FlashDevice>
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<Device>
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<Pos>1</Pos>
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<Vendor>Macronix</Vendor>
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<Family>SPI Serial Flash</Family>
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<Name>MX25L12833F</Name>
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<IDCode>0x18</IDCode>
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<Package>8-pin SOP</Package>
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<Operation>Erase,Program,Verify</Operation>
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<File>{bitstream_file}</File>
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<AddressBase>0x00000000</AddressBase>
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<EndAddress>0x000F0000</EndAddress>
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<DeviceSize>128</DeviceSize>
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<DataSize>1016029</DataSize>
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<NumberOfDevices>1</NumberOfDevices>
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<ReInitialize value="FALSE"/>
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</Device>
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</FlashDevice>
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<FPGADevice>
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<Device>
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<Pos>1</Pos>
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<Name></Name>
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<File>{bitstream_file}</File>
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<LocalChainList>
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<LocalDevice index="-99"
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name="Unknown"
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file="{bitstream_file}"/>
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</LocalChainList>
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<Option>
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<SVFVendor>JTAG STANDARD</SVFVendor>
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</Option>
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</Device>
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</FPGADevice>
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</FPGALoader>
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</Device>
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</Chain>
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<ProjectOptions>
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<Program>SEQUENTIAL</Program>
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<Process>ENTIRED CHAIN</Process>
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<OperationOverride>No Override</OperationOverride>
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<StartTAP>TLR</StartTAP>
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<EndTAP>TLR</EndTAP>
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<DisableCheckBoard value="TRUE"/>
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<VerifyUsercode value="FALSE"/>
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<TCKDelay>3</TCKDelay>
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</ProjectOptions>
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<CableOptions>
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<CableName>USB2</CableName>
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<PortAdd>FTUSB-0</PortAdd>
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<USBID>Lattice CrossLink-NX Eval Board A Location 0000 Serial FT4J4IK9A</USBID>
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</CableOptions>
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</ispXCF>
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"""
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if mode == "direct":
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xcf_template = xcf_template_direct
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if mode == "flash":
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xcf_template = xcf_template_flash
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return LatticeProgrammer(xcf_template)
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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import litex_boards.platforms.antmicro_sdi_mipi_video_converter
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from litex.soc.cores.ram import NXLRAM
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from litex.soc.cores.clock import NXPLL
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from litex.build.generic_platform import *
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.build.lattice.oxide import oxide_args, oxide_argdict
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from litex.build.lattice.radiant import radiant_build_argdict, radiant_build_args
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kB = 1024
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mB = 1024*kB
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_por = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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# Built in OSC
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self.submodules.hf_clk = NXOSCA()
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hf_clk_freq = 25e6
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self.hf_clk.create_hf_clk(self.cd_por, hf_clk_freq)
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.submodules.sys_pll = sys_pll = NXPLL(platform=platform, create_output_port_clocks=True)
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sys_pll.register_clkin(self.cd_por.clk, hf_clk_freq)
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sys_pll.create_clkout(self.cd_sys, sys_clk_freq)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~self.sys_pll.locked | ~por_done)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {
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"rom": 0x00000000,
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"sram": 0x40000000,
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"main_ram": 0x60000000,
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"csr": 0xf0000000,
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}
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def __init__(self, sys_clk_freq=int(75e6), device="LIFCL-40-9BG256C", toolchain="radiant", with_led_chaser=True, **kwargs):
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platform = litex_boards.platforms.antmicro_sdi_mipi_video_converter.Platform(
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device=device, toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SoCCore -----------------------------------------_----------------------------------------
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# Disable Integrated SRAM since we want to instantiate LRAM specifically for it
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kwargs["integrated_sram_size"] = 0
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident="LiteX SoC on Crosslink-NX Evaluation Board", **kwargs)
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# 128KB LRAM (used as SRAM) ---------------------------------------------------------------
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self.submodules.spram = NXLRAM(32, 64*kB)
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self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=16*kB))
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self.submodules.main_ram = NXLRAM(32, 64*kB)
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self.bus.add_slave("main_ram", self.main_ram.bus, SoCRegion(origin=self.mem_map["main_ram"], size=64*kB))
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads=Cat(*[platform.request("user_led", i) for i in range(2)]),
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sys_clk_freq=sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Crosslink-NX Eval Board")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--toolchain", default="radiant", help="FPGA toolchain (radiant or prjoxide).")
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target_group.add_argument("--device", default="LIFCL-40-9BG256C", help="FPGA device (LIFCL-40-9BG400C, LIFCL-40-8BG400CES, or LIFCL-40-8BG400CES2).")
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target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
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target_group.add_argument("--programmer", default="radiant", help="Programmer (radiant or ecpprog).")
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target_group.add_argument("--prog-target", default="direct", help="Programming Target (direct or flash).")
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builder_args(parser)
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soc_core_args(parser)
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oxide_args(parser)
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radiant_build_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq=int(float(args.sys_clk_freq)),
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device=args.device,
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toolchain=args.toolchain,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = oxide_argdict(args) if args.toolchain == "oxide" else radiant_build_argdict(args)
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if args.build:
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builder.build(**builder_kargs)
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if args.load:
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prog = soc.platform.create_programmer(args.prog_target, args.programmer)
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if args.programmer == "ecpprog" and args.prog_target == "flash":
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prog.flash(address=args.address,
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bitstream=builder.get_bitstream_filename(mode="sram"))
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else:
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if args.programmer == "radiant":
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os.system("sudo modprobe -rf ftdi_sio")
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.programmer == "radiant":
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os.system("sudo modprobe ftdi_sio")
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if __name__ == "__main__":
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main()
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