Merge pull request #416 from shenki/artix-dc-scm
Add Antmicro Artix DC-SCM board
This commit is contained in:
enjoy-digital
GitHub
commit
feff243f8f
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk100", 0, Pins("C18"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("T20"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("U20"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("W20"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("R19")),
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Subsignal("rx", Pins("P19")),
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IOStandard("LVCMOS33"),
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),
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("serial", 1,
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Subsignal("tx", Pins("U21")),
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Subsignal("rx", Pins("T21")),
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IOStandard("LVCMOS33"),
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),
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# DDR3 SDRAM (voltage changed from 1.5V to 1.35V)
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("ddram", 0,
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Subsignal("a", Pins(
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"M2 M5 M3 M1 L6 P1 N3 N2",
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"M6 R1 L5 N5 N4 P2 P6"),
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IOStandard("SSTL135")),
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Subsignal("ba", Pins("L3 K6 L4"), IOStandard("SSTL135")),
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Subsignal("ras_n", Pins("J4"), IOStandard("SSTL135")),
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Subsignal("cas_n", Pins("K3"), IOStandard("SSTL135")),
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Subsignal("we_n", Pins("L1"), IOStandard("SSTL135")),
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Subsignal("dm", Pins("G3 F1"), IOStandard("SSTL135")),
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Subsignal("dq", Pins(
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"G2 H4 H5 J1 K1 H3 H2 J5",
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"E3 B2 F3 D2 C2 A1 E2 B1"),
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IOStandard("SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins("K2 E1"),
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IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_n", Pins("J2 D1"),
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IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("clk_p", Pins("P5"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_n", Pins("P4"), IOStandard("DIFF_SSTL135")),
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Subsignal("cke", Pins("J6"), IOStandard("SSTL135")),
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Subsignal("odt", Pins("K4"), IOStandard("SSTL135")),
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Subsignal("reset_n", Pins("G1"), IOStandard("SSTL135")),
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Misc("SLEW=FAST"),
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),
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# eMMC - there are pullups on the board so we don't enable them here
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("sdcard", 0,
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Subsignal("data", Pins("P17 W17 R18 V18")),
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Subsignal("cmd", Pins("Y19")),
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Subsignal("clk", Pins("Y18")),
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#Subsignal("cd", Pins(),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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# RGMII Ethernet
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("eth_ref_clk", 0, Pins("H19"), IOStandard("LVCMOS33")), # 125 MHz if enabled?
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("eth_clocks", 0,
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Subsignal("tx", Pins("J19")),
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Subsignal("rx", Pins("K19")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("N18"), IOStandard("LVCMOS33")),
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Subsignal("int_n", Pins("N20"), IOStandard("LVCMOS33")),
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Subsignal("mdio", Pins("M21"), IOStandard("LVCMOS33")),
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Subsignal("mdc", Pins("N22"), IOStandard("LVCMOS33")),
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Subsignal("rx_ctl", Pins("M22"), IOStandard("LVCMOS33")),
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Subsignal("rx_data", Pins("L20 L21 K21 K22"), IOStandard("LVCMOS33")),
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Subsignal("tx_ctl", Pins("J22"), IOStandard("LVCMOS33")),
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Subsignal("tx_data", Pins("G20 H20 H22 J21"), IOStandard("LVCMOS33")),
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),
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# PCIe
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("pcie_x1", 0,
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# Subsignal("rst_n", Pins(""), IOStandard("LVCMOS33")),
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Subsignal("clk_p", Pins("F6")),
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Subsignal("clk_n", Pins("E6")),
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Subsignal("rx_p", Pins("B8")),
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Subsignal("rx_n", Pins("A8")),
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Subsignal("tx_p", Pins("B4")),
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Subsignal("tx_n", Pins("A4"))
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),
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# USB ULPI
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("ulpi_clock", 0, Pins("W19"), IOStandard("LVCMOS33")),
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("ulpi", 0,
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Subsignal("data", Pins("AB18 AA18 AA19 AB20 AA20 AB21 AA21 AB22")),
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Subsignal("dir", Pins("W21")),
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Subsignal("stp", Pins("Y22")),
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Subsignal("nxt", Pins("W22")),
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Subsignal("rst", Pins("V20")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST")
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),
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("ulpi_clock", 1, Pins("V4"), IOStandard("LVCMOS33")),
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("ulpi", 1,
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Subsignal("data", Pins("AB2 AA3 AB3 Y4 AA4 AB5 AA5 AB6")),
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Subsignal("dir", Pins("AB7")),
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Subsignal("stp", Pins("AA6")),
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Subsignal("nxt", Pins("AB8")),
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Subsignal("rst", Pins("AA8")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, device="xc7a100tfgg484-1", toolchain="vivado"):
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XilinxPlatform.__init__(self, device, _io, toolchain=toolchain)
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# self.toolchain.bitstream_commands = \
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# ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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# self.toolchain.additional_commands = \
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# ["write_cfgmem -force -format bin -interface spix4 -size 16 "
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# "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 35]")
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def create_programmer(self):
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bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"
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return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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@ -0,0 +1,172 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Antmicro <www.antmicro.com>
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# Copyright (c) 2022 IBM Corp.
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import math
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from migen import *
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from litex_boards.platforms import antmicro_artix_dc_scm
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT41K128M16
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from litedram.phy import s7ddrphy
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from liteeth.phy import LiteEthS7PHYRGMII
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from litepcie.phy.s7pciephy import S7PCIEPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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self.clock_domains.cd_ulpi0 = ClockDomain()
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self.clock_domains.cd_ulpi1 = ClockDomain()
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# ulpi0 clock domain (60MHz from ulpi0)
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self.comb += self.cd_ulpi0.clk.eq(platform.request("ulpi_clock", 0))
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# ulpi1 clock domain (60MHz from ulpi1)
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self.comb += self.cd_ulpi1.clk.eq(platform.request("ulpi_clock", 1))
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# # #
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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# self.comb += pll.reset.eq(~platform.request("cpu_reset") | self.rst)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4 * sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4 * sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, *, device, with_pcie, with_etherbone, with_ethernet, with_sdram, eth_dynamic_ip,
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eth_reset_time, toolchain="vivado", sys_clk_freq=int(100e6), eth_ip="192.168.1.120", **kwargs):
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platform = antmicro_artix_dc_scm.Platform(device=device, toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Artix DC-SCM", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K128M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthS7PHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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hw_reset_cycles = math.ceil(float(eth_reset_time) * self.sys_clk_freq)
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)
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets main_ethphy_eth_rx_clk_ibuf]")
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
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data_width = 128,
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bar0_size = 0x20000)
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self.add_csr("pcie_phy")
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Artix DC-SCM")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado or symbiflow).")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--flash", action="store_true", help="Flash bitstream")
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target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
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target_group.add_argument("--device", default="xc7a100tfgg484-1", choices=["xc7a100tfgg484-1", "xc7a15tfgg484-1"])
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target_group.add_argument("--with-pcie", action="store_true", help="Add PCIe")
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ethopts = target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Add Ethernet")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Add EtherBone")
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target_group.add_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address")
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target_group.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting")
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target_group.add_argument("--eth-reset-time", default="10e-3", help="Duration of Ethernet PHY reset")
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target_group.add_argument("--with-sdram", action="store_true", help="Add SDRAM")
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target_group.add_argument("--with-emmc", action="store_true", help="Add eMMC")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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assert not (args.with_etherbone and args.eth_dynamic_ip)
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soc = BaseSoC(
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toolchain = args.toolchain,
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device = args.device,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_pcie = args.with_pcie,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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with_sdram = args.with_sdram,
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eth_reset_time = args.eth_reset_time,
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**soc_core_argdict(args)
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)
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if args.with_emmc:
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soc.add_sdcard(software_debug=False)
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builder = Builder(soc, **builder_argdict(args))
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builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
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if args.build:
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builder.build(**builder_kwargs)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, builder.get_bitstream_filename(mode="flash"))
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if __name__ == "__main__":
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main()
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