targets/fomu: base it on iCEBreaker target + USB-ACM.
This uniformizes Fomu target with others, provide a simple example of LiteX SoC on Fomu and will ease maintenance.
This commit is contained in:
Florent Kermarrec
parent
79ef091a06
commit
fff20f7532
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@ -5,295 +5,160 @@
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#
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# Copyright (c) 2019 Sean Cross <sean@xobs.io>
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# Copyright (c) 2018 David Shah <dave@ds0.me>
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import sys
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.soc.cores import up5kspram
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.integration.builder import Builder, builder_argdict, builder_args
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from litex.soc.integration.soc_core import soc_core_argdict, soc_core_args
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from litex.soc.integration.doc import AutoDoc
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from litex_boards.platforms import fomu_pvt
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from valentyusb.usbcore import io as usbio
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from valentyusb.usbcore.cpu import dummyusb, epfifo, eptri
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from litex.soc.cores.up5kspram import Up5kSPRAM
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from litex.soc.cores.spi_flash import SpiFlash
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from litex.soc.cores.clock import iCE40PLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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import os, shutil, subprocess
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kB = 1024
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mB = 1024*kB
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module, AutoDoc):
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"""Fomu Clock Resource Generator
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Fomu is a USB device, which means it must have a 12 MHz clock. Valentyusb
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oversamples the clock by 4x, which drives the requirement for a 48 MHz clock.
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The ICE40UP5k is a relatively low speed grade of FPGA that is incapable of
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running the entire design at 48 MHz, so the majority of the logic is placed
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in the 12 MHz domain while only critical USB logic is placed in the fast
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48 MHz domain.
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Fomu has a 48 MHz crystal on it, which provides the raw clock input. This
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signal is fed through the ICE40 PLL in order to divide it down into a 12 MHz
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signal and keep the clocks within 1ns of phase. Earlier designs used a simple
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flop, however this proved unreliable when the FPGA became very full.
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The following clock domains are available on this design:
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+---------+------------+---------------------------------+
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| Name | Frequency | Description |
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+=========+============+=================================+
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| usb_48 | 48 MHz | Raw USB signals and pulse logic |
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+---------+------------+---------------------------------+
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| usb_12 | 12 MHz | USB control logic |
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+---------+------------+---------------------------------+
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| sys | 12 MHz | System CPU and wishbone bus |
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+---------+------------+---------------------------------+
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"""
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def __init__(self, platform):
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clk48_raw = platform.request("clk48")
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clk12 = Signal()
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reset_delay = Signal(12, reset=4095)
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self.clock_domains.cd_por = ClockDomain()
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self.reset = Signal()
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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assert sys_clk_freq == 12e6
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.clock_domains.cd_usb_48 = ClockDomain()
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platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/12e6)
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platform.add_period_constraint(self.cd_usb_12.clk, 1e9/12e6)
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platform.add_period_constraint(clk48_raw, 1e9/48e6)
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# # #
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# POR reset logic- POR generated from sys clk, POR logic feeds sys clk
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# reset.
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self.comb += [
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self.cd_por.clk.eq(self.cd_sys.clk),
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self.cd_sys.rst.eq(reset_delay != 0),
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self.cd_usb_12.rst.eq(reset_delay != 0),
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]
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# Clk/Rst
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clk48 = platform.request("clk48")
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platform.add_period_constraint(clk48, 1e9/48e6)
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# POR reset logic- POR generated from sys clk, POR logic feeds sys clk
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# reset.
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self.comb += [
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self.cd_usb_48.rst.eq(reset_delay != 0),
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]
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# Power On Reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(ClockSignal())
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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self.comb += self.cd_usb_48.clk.eq(clk48_raw)
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self.specials += Instance(
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"SB_PLL40_CORE",
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# Parameters
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p_DIVR = 0,
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p_DIVF = 15,
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p_DIVQ = 5,
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p_FILTER_RANGE = 1,
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p_FEEDBACK_PATH = "SIMPLE",
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p_DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED",
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p_FDA_FEEDBACK = 15,
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p_DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED",
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p_FDA_RELATIVE = 0,
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p_SHIFTREG_DIV_MODE = 1,
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p_PLLOUT_SELECT = "GENCLK_HALF",
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p_ENABLE_ICEGATE = 0,
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# IO
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i_REFERENCECLK = clk48_raw,
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o_PLLOUTCORE = clk12,
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# o_PLLOUTGLOBAL = clk12,
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#i_EXTFEEDBACK,
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#i_DYNAMICDELAY,
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#o_LOCK,
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i_BYPASS = 0,
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i_RESETB = 1,
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#i_LATCHINPUTVALUE,
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#o_SDO,
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#i_SDI,
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)
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self.comb += self.cd_sys.clk.eq(clk12)
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self.comb += self.cd_usb_12.clk.eq(clk12)
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self.sync.por += \
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If(reset_delay != 0,
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reset_delay.eq(reset_delay - 1)
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)
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self.specials += AsyncResetSynchronizer(self.cd_por, self.reset)
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# USB PLL
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self.submodules.pll = pll = iCE40PLL()
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pll.clko_freq_range = ( 12e6, 275e9) # FIXME: improve iCE40PLL to avoid lowering clko_freq_min.
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pll.register_clkin(clk48, 48e6)
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pll.create_clkout(self.cd_usb_12, 12e6, with_reset=False)
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self.comb += self.cd_usb_48.clk.eq(clk48)
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self.specials += AsyncResetSynchronizer(self.cd_usb_12, ~por_done | ~pll.locked)
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self.specials += AsyncResetSynchronizer(self.cd_usb_48, ~por_done | ~pll.locked)
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# Sys Clk
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self.comb += self.cd_sys.clk.eq(self.cd_usb_12.clk)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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"""A SoC on Fomu, optionally with a softcore CPU"""
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# Create a default CSR map to prevent values from getting reassigned.
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# This increases consistency across litex versions.
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SoCCore.csr_map = {
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"ctrl": 0, # provided by default (optional)
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"crg": 1, # user
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"uart_phy": 2, # provided by default (optional)
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"uart": 3, # provided by default (optional)
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"identifier_mem": 4, # provided by default (optional)
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"timer0": 5, # provided by default (optional)
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"cpu_or_bridge": 8,
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"usb": 9,
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"picorvspi": 10,
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"touch": 11,
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"reboot": 12,
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"rgb": 13,
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"version": 14,
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}
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# Statically-define the memory map, to prevent it from shifting across
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# various litex versions.
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SoCCore.mem_map = {
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"rom": 0x00000000, # (default shadow @0x80000000)
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"sram": 0x10000000, # (default shadow @0xa0000000)
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"spiflash": 0x20000000, # (default shadow @0xa0000000)
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"main_ram": 0x40000000, # (default shadow @0xc0000000)
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"csr": 0xe0000000, # (default shadow @0x60000000)
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}
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def __init__(self, board,
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pnr_placer="heap", pnr_seed=0, usb_core="dummyusb", usb_bridge=False,
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use_dsp=True, **kwargs):
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"""Create a basic SoC for Fomu.
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Create a basic SoC for Fomu, including a 48 MHz and 12 MHz clock
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domain called `usb_48` and `usb_12`. The `sys` frequency will
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run at 12 MHz.
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The USB core will optionally have a bridge to the Wishbone bus.
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Args:
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board (str): Which Fomu board to build for: pvt, evt, or hacker
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pnr_placer (str): Which placer to use in nextpnr
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pnr_seed (int): Which seed to use in nextpnr
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usb_core (str): The name of the USB core to use, if any: dummyusb, epfifo, eptri
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usb_bridge (bool): Whether to include a USB-to-Wishbone bridge
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Raises:
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ValueError: If either the `usb_core` or `board` are unrecognized
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Returns:
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Newly-constructed SoC
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"""
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if board == "pvt":
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from litex_boards.platforms.fomu_pvt import Platform
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elif board == "hacker":
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from litex_boards.platforms.fomu_hacker import Platform
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elif board == "evt":
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from litex_boards.platforms.fomu_evt import Platform
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else:
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raise ValueError("unrecognized fomu board: {}".format(board))
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platform = Platform()
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if "cpu_type" not in kwargs:
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kwargs["cpu_type"] = None
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kwargs["cpu_variant"] = None
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clk_freq = int(12e6)
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if "with_uart" not in kwargs:
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kwargs["with_uart"] = False
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if "with_ctrl" not in kwargs:
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kwargs["with_ctrl"] = False
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mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
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def __init__(self, bios_flash_offset, **kwargs):
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kwargs["uart_name"] = "usb_acm" # Enforce UART to USB-ACM
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sys_clk_freq = int(12e6)
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platform = fomu_pvt.Platform()
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# Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
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kwargs["integrated_sram_size"] = 0
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SoCCore.__init__(self, platform, clk_freq, **kwargs)
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kwargs["integrated_rom_size"] = 0
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self.submodules.crg = _CRG(platform)
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# Set CPU variant / reset address
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kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
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# UP5K has single port RAM, which is a dedicated 128 kilobyte block.
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# Use this as CPU RAM.
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spram_size = 128*1024
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self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
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self.register_mem("sram", self.mem_map["sram"], self.spram.bus, spram_size)
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# Serial -----------------------------------------------------------------------------------
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# FIXME: do proper install of ValentyUSB.
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# FIXME: replace IoBuf with https://github.com/im-tomu/valentyusb/blob/master/valentyusb/usbcore/io.py#L13-L61.
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os.system("git clone https://github.com/gregdavill/valentyusb -b hw_cdc_eptri")
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sys.path.append("valentyusb")
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if usb_core is not None:
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# Add USB pads. We use DummyUsb, which simply enumerates as a USB
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# device. Then all interaction is done via the wishbone bridge.
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usb_pads = platform.request("usb")
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usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
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if usb_core == "dummyusb":
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self.submodules.usb = dummyusb.DummyUsb(usb_iobuf, debug=usb_bridge)
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elif usb_core == "epfifo":
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self.submodules.usb = epfifo.PerEndpointFifo(usb_iobuf, debug=usb_bridge)
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elif usb_core == "eptri":
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self.submodules.usb = eptri.TriEndpointInterface(usb_iobuf, debug=usb_bridge)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Fomu",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
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self.submodules.spram = Up5kSPRAM(size=128*kB)
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self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128*kB))
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# SPI Flash --------------------------------------------------------------------------------
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self.add_spi_flash(mode="1x", dummy_cycles=8)
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# Add ROM linker region --------------------------------------------------------------------
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self.bus.add_region("rom", SoCRegion(
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origin = self.mem_map["spiflash"] + bios_flash_offset,
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size = 32*kB,
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linker = True)
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)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led_n"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Flash --------------------------------------------------------------------------------------------
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def flash(bios_flash_offset):
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from litex.build.dfu import DFUProg
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prog = DFUProg(vid="1209", pid="5bf0")
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bitstream = open("build/fomu_pvt/gateware/fomu_pvt.bin", "rb")
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bios = open("build/fomu_pvt/software/bios/bios.bin", "rb")
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image = open("build/fomu_pvt/image.bin", "wb")
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# Copy bitstream at 0x00000000
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for i in range(0x00000000, 0x0020000):
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b = bitstream.read(1)
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if not b:
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image.write(0xff.to_bytes(1, "big"))
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else:
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raise ValueError("unrecognized usb_core: {}".format(usb_core))
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if usb_bridge:
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self.add_wb_master(self.usb.debug_bridge.wishbone)
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# Override default LiteX's yosys/build templates
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assert hasattr(platform.toolchain, "yosys_template")
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assert hasattr(platform.toolchain, "build_template")
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platform.toolchain.yosys_template = [
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"{read_files}",
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"attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
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"synth_ice40 -json {build_name}.json -top {build_name}",
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]
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platform.toolchain.build_template = [
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"yosys -q -l {build_name}.rpt {build_name}.ys",
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"nextpnr-ice40 --json {build_name}.json --pcf {build_name}.pcf --asc {build_name}.txt \
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--pre-pack {build_name}_pre_pack.py --{architecture} --package {package}",
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"icepack {build_name}.txt {build_name}.bin"
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]
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# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
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# The "-reult" adds an additional LUT pass to pack more stuff in,
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# and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
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# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
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# This increases density, and lets us use the FPGA more efficiently.
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platform.toolchain.yosys_template[2] += " -relut -abc2 -dffe_min_ce_use 4 -relut"
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if use_dsp:
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platform.toolchain.yosys_template[2] += " -dsp"
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# Disable final deep-sleep power down so firmware words are loaded
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# onto softcore's address bus.
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platform.toolchain.build_template[2] = "icepack -s {build_name}.txt {build_name}.bin"
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# Allow us to set the nextpnr seed
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platform.toolchain.build_template[1] += " --seed " + str(pnr_seed)
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if pnr_placer is not None:
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platform.toolchain.build_template[1] += " --placer {}".format(pnr_placer)
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class USBSoC(BaseSoC):
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"""A SoC for Fomu with interrupts for a softcore CPU"""
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interrupt_map = {
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"usb": 3,
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}
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interrupt_map.update(SoCCore.interrupt_map)
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image.write(b)
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# Copy bios at 0x00020000
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for i in range(0x00000000, 0x00010000):
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b = bios.read(1)
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if not b:
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image.write(0xff.to_bytes(1, "big"))
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else:
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image.write(b)
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bitstream.close()
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bios.close()
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image.close()
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prog.load_bitstream("build/fomu_pvt/image.bin")
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# Build --------------------------------------------------------------------------------------------
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def add_dfu_suffix(fn):
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fn_base, _ext = os.path.splitext(fn)
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fn_dfu = fn_base + '.dfu'
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shutil.copyfile(fn, fn_dfu)
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subprocess.check_call(['dfu-suffix', '--pid', '1209', '--vid', '5bf0', '--add', fn_dfu])
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Fomu")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--board", choices=["evt", "pvt", "hacker"], required=True, help="Build for a particular hardware board")
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parser.add_argument("--seed", default=0, help="Seed to use in Nextpnr")
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parser.add_argument("--placer", default="heap", choices=["sa", "heap"], help="Which placer to use in Nextpnr")
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parser.add_argument("--bios-flash-offset", default=0x60000, help="BIOS offset in SPI Flash")
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parser.add_argument("--flash", action="store_true", help="Flash Bitstream")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(board=args.board, pnr_placer=args.placer, pnr_seed=args.seed, debug=True, **soc_core_argdict(args))
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soc = BaseSoC(args.bios_flash_offset, **soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.flash:
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flash(args.bios_flash_offset)
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
|
|||
Loading…
Reference in New Issue