Commit Graph

11 Commits

Author SHA1 Message Date
Florent Kermarrec b53b79821e platforms: Expose toolchain parameter on all platforms to ease switching to alternative/open-source toolchains. 2022-02-14 11:35:18 +01:00
Florent Kermarrec 1abb03e514 tang_nano_4k: Review/Cleanup:
- Revert abstractions on clk_name/period: Too much abstraction to avoid duplications makes the code more difficult to read.
ex:
  - When constraining clk27, frequency is already in the name.
  - In the target, we want to know we are using clk27 as the main clk.
  - We need a default sys_clk_freq for project only importing BaseSoC.
- Revert SPI Flash import (for consistency with other targets).
- Keep VexRiscv as default CPU since this target is able to run it and also for consistency with other targets.
2022-01-24 18:46:51 +01:00
Ilia Sergachev f078e55bb1 tang nano 4k: fix removed default_clk_period, fix do_finalize signature 2022-01-23 16:47:20 +01:00
Ilia Sergachev 6238052b10 tang nano 4k: disable spi flash with gowin emcu, cleanup 2022-01-23 16:10:46 +01:00
Florent Kermarrec d5eea94289 sispeed_tang_nano_4k: Avoid IOStandard constraints on HyperRAM (Not present in example designs). 2021-09-20 11:46:10 +02:00
Florent Kermarrec 5190c9c869 sipeed_tang_nano_4k: Initial Video Out support.
With colorbars for now, need to free up BRAMS for Video Terminal (or finish HyperRAM support).
2021-09-20 09:32:20 +02:00
Florent Kermarrec 376a836583 sipeed_tang_nano: Add SPI Flash, Enable CPU and use new external SPI Flash support from OpenFPGALoader.
./sipeed_tang_nano_4k.py --cpu-type=vexriscv --cpu-variant=lite --build --flash

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 (c) Copyright 2012-2021 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Sep 17 2021 15:54:08
 BIOS CRC passed (6cc6de6d)

 Migen git sha1: a5bc262
 LiteX git sha1: 46cd9c5a

--=============== SoC ==================--
CPU:		VexRiscv_Lite @ 27MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		64KiB
SRAM:		8KiB
FLASH:		4096KiB

--========== Initialization ============--

Initializing W25Q32 SPI Flash @0x80000000...
SPI Flash clk configured to 13 MHz
Memspeed at 0x80000000 (Sequential, 4.0KiB)...
   Read speed: 1.3MiB/s
Memspeed at 0x80000000 (Random, 4.0KiB)...
   Read speed: 521.9KiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
2021-09-17 15:57:55 +02:00
Gwenhael Goavec-Merou fed36afaba platforms/sipeed_tang_nano_4k: fix period computation 2021-09-15 06:46:29 +02:00
Gwenhael Goavec-Merou 945e48ea83 platforms/sipeed_tang_nano_4k: add P6 and P7 connectors 2021-09-09 11:35:14 +02:00
Florent Kermarrec 8d91489756 tang_nano_4k: Add more IOs. 2021-09-09 11:23:20 +02:00
Florent Kermarrec 88534c6689 tang_nano_4k: Fix typo in sipeed. 2021-09-08 23:02:39 +02:00