Florent Kermarrec
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1f88a9d5ec
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platforms: make sure clocks inputs are constraints on all platforms.
Also use new loose lookup_request to simplify constraints.
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2020-05-05 11:45:41 +02:00 |
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Florent Kermarrec
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86648ec7d8
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platforms/vcu118: rename ddram_second_channel to ddram:1.
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2020-05-05 09:54:11 +02:00 |
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Florent Kermarrec
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2cf3c3e845
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platforms: cosmetic cleanups.
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2020-04-09 23:05:13 +02:00 |
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Florent Kermarrec
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95e1a05bf1
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platforms/Ultrascale: avoid unnecessary {{}} on INTERNAL_VREF.
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2020-03-09 09:29:49 +01:00 |
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Florent Kermarrec
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d4460c11a5
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platforms/kcu105/vcu118: remove PRE_EMPHASIS/EQUALIZATION on dm.
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2020-02-27 10:43:41 +01:00 |
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Florent Kermarrec
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e516ff3452
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vcu118/ddram: use similar IO settings than Xilinx's MIG, comment unused pins.
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2020-02-26 10:16:51 +01:00 |
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Florent Kermarrec
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83d2c71099
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platforms/vcu118: add missing Internal Vref configuration on DDR4 C1/C2 banks
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2020-02-25 18:32:42 +01:00 |
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Florent Kermarrec
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f279fe9d33
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vc707: cleanup platform/targets, remove Ethernet support (no Ethernet pads defined)
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2020-02-25 10:35:18 +01:00 |
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Florent Kermarrec
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88a1f80db1
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vc707/vcu118: use proper copyrights
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2020-02-25 09:03:52 +01:00 |
Fei Gao
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373e74f435
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add new board files for VC707 and VCU118, only specified limited ports for VCU118, including clock, reset and DDR4
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2020-02-24 14:20:47 -05:00 |